High-level synthesis under multi-cycle interconnect delay

Authors:
Jinhwan Jeon;Daehong Kim;Dongwan Shin;Kiyoung Choi
Affiliations:
School of EECS, Seoul Nat'l University, Seoul 151-742, Korea;School of EECS, Seoul Nat'l University, Seoul 151-742, Korea;Dept. of ICS, University of California, Irvine, CA;School of EECS, Seoul Nat'l University, Seoul 151-742, Korea
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

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Abstract

As process technology goes into deep submicron range, interconnect delay becomes dominant among overall system delay, occupying most of the system clock cycle time. Interconnect delay is now a crucial factor that needs to be considered even during high-level synthesis. In this paper, we propose a concurrent scheduling and binding algorithm that takes interconnect delay into account. We first define our distributed target architecture, which minimizes the effect of interconnect delay on clock cycle time. We no longer assume that interconnect delay between functional units is a part of one clock cycle. Interconnect delay can span over multiple clock cycles. We incorporate the concept of multi-cycle interconnect delay into scheduling and binding process, to reduce the critical path length and therefore the system latency. We show that by introducing interconnect delay, we can obtain latency improvement of up to 54 % and of 37% on the average.