Transformation-based high-level synthesis of fault-tolerant ASICs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Timing models for high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Performance-driven interconnection optimization for microarchitecture synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Harmonic scheduling of linear recurrences for digital filter design
EURO-DAC '92 Proceedings of the conference on European design automation
Semantics and synthesis of signals in behavioral VHDL
EURO-DAC '92 Proceedings of the conference on European design automation
Utilization of multiport memories in data path synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Comparative design validation based on event pattern mappings
DAC '93 Proceedings of the 30th international Design Automation Conference
High-level transformations for minimizing syntactic variances
DAC '93 Proceedings of the 30th international Design Automation Conference
High-level synthesis of fault-secure microarchitectures
DAC '93 Proceedings of the 30th international Design Automation Conference
Integrating program transformations in the memory-based synthesis of image and video algorithms
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Condition graphs for high-quality behavioral synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Minimization of memory traffic in high-level synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Sequencer-based data path synthesis of regular iterative algorithms
DAC '94 Proceedings of the 31st annual Design Automation Conference
Structured design methodology for high-level design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Area-efficient fault detection during self-recovering microarchitecture synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
A performance evaluator for parameterized ASIC architectures
EURO-DAC '94 Proceedings of the conference on European design automation
A new technique for exploiting regularity in data path synthesis
EURO-DAC '94 Proceedings of the conference on European design automation
EURO-DAC '94 Proceedings of the conference on European design automation
Using C to write portable CMOS VLSI module generators
EURO-DAC '94 Proceedings of the conference on European design automation
GC: the data-flow graph format of synchronous programming
IR '95 Papers from the 1995 ACM SIGPLAN workshop on Intermediate representations
Register minimization beyond sharing among variables
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Behavioral synthesis methodology for HDL-based specification and validation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Equivalence checking of datapaths based on canonical arithmetic expressions
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Timing constraint specification and synthesis in behavioral VHDL
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Background memory management for dynamic data structure intensive processing systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Architectural partitioning of control memory for application specific programmable processors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An optimal clock period selection method based on slack minimization criteria
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Domain-specific high-level modeling and synthesis for ATM switch design using VHDL
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis of reusable DSP cores based on multiple behaviors
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock-driven performance optimization in interactive behavioral synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Heterogeneous built-in resiliency of application specific programmable processors
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Optimal Data Scheduling for Uniform Multidimensional Applications
IEEE Transactions on Computers
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Storage optimization by replacing some flip-flops with latches
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Assignment of storage values to sequential read-write memories
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Clock optimization for high-performance pipelined design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
BDD-based testability estimation of VHDL designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Towards maximising the use of structural VHDL for synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
System design using an integrated specification and performance modeling methodology
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
How datapath allocation affects controller delay
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An efficient representation for formal synthesis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Low power high level synthesis by increasing data correlation
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Exploiting off-chip memory access modes in high-level synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions
DAC '98 Proceedings of the 35th annual Design Automation Conference
Communication synthesis and HW/SW integration for embedded system design
Proceedings of the 6th international workshop on Hardware/software codesign
Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Transforming control-flow intensive designs to facilitate power management
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical performance-driven module binding in high-level synthesis
Proceedings of the 11th international symposium on System synthesis
Register Allocation—A Hierarchical Reduction Approach
Journal of VLSI Signal Processing Systems
The case for a configure-and-execute paradigm
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
A unified formal model of ISA and FSMD
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
An efficient multi-view design model for real-time interactive synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Equivalent design representations and transformations for interactive scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
FSMD functional partitioning for low power
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Synthesis of controllers for full testability of integrated datapath-controller pairs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Channel-based behavioral test synthesis for improved module reachability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Soft scheduling in high level synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multiway FPGA partitioning by fully exploiting design hierarchy
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis
Proceedings of the 37th Annual Design Automation Conference
System-level data format exploration for dynamically allocated data structures
Proceedings of the 37th Annual Design Automation Conference
Synthesis-for-testability of controller-datapath pairs that use gated clocks
Proceedings of the 37th Annual Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Efficient resource arbitration in reconfigurable computing environments
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Detecting undetectable controller faults using power analysis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Improving the schedule quality of static-list time-constrained scheduling (poster paper)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Allocation of FIFO structures in RTL data paths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A codesign back-end approach for embedded system design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level library mapping for memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers
Proceedings of the conference on Design, automation and test in Europe
Static memory allocation by pointer analysis and coloring
Proceedings of the conference on Design, automation and test in Europe
Hardware/software partitioning with integrated hardware design space exploration
Proceedings of the conference on Design, automation and test in Europe
The design of an asynchronous VHDL synthesizer
Proceedings of the conference on Design, automation and test in Europe
Layout-driven high level synthesis for FPGA based architectures
Proceedings of the conference on Design, automation and test in Europe
A systems theoretic approach to behavioural modeling and simulation of analog functional blocks
Proceedings of the conference on Design, automation and test in Europe
Usage-based characterization of complex functional blocks for reuse in behavioral synthesis
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A bypass scheme for core-based system fault testing
Proceedings of the conference on Design, automation and test in Europe
Thread partitioning method for hardware compiler bach
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits
IEEE Transactions on Computers
A C-based synthesis system, Bach, and its application (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An RTL design-space exploration method for high-level applications
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
High-level synthesis under multi-cycle interconnect delay
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An algorithm for synthesis of large time-constrained heterogeneous adaptive systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Speculation techniques for high level synthesis of control intensive designs
Proceedings of the 38th annual Design Automation Conference
A universal client for distributed networked design and computing
Proceedings of the 38th annual Design Automation Conference
Statistical design space exploration for application-specific unit synthesis
Proceedings of the 38th annual Design Automation Conference
Integrated test of interacting controllers and datapaths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Conditional speculation and its effects on performance and area for high-level snthesis
Proceedings of the 14th international symposium on Systems synthesis
Soft-cores generation by instruction set analysis
Proceedings of the 14th international symposium on Systems synthesis
Efficient integration of behavioral synthesis within existing design flows
ISSS '00 Proceedings of the 13th international symposium on System synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Coordinated transformations for high-level synthesis of high performance microprocessor blocks
Proceedings of the 39th annual Design Automation Conference
Readings in hardware/software co-design
Memory management for embedded network applications
Readings in hardware/software co-design
A processor-coprocessor architecture for high end video applications
Readings in hardware/software co-design
Formal Methods in System Design
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Data memory design considering effective bitwidth for low-energy embedded systems
Proceedings of the 15th international symposium on System Synthesis
A methodology for verifying memory access protocols in behavioral synthesis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A system for synthesizing optimized FPGA hardware from MATLAB
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Design of Processor Arrays for Reconfigurable Architectures
The Journal of Supercomputing
Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach
Journal of Electronic Testing: Theory and Applications
Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
Net Scheduling in High-Level Synthesis
IEEE Design & Test
Optimizing Power in ASIC Behavioral Synthesis
IEEE Design & Test
Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs
IEEE Design & Test
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
Global memory mapping for FPGA-based reconfigurable systems
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Formal Synthesis at the Algorithmic Level
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Complex Reactive Control with Simple Synchronous Models
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Computer
Compilation for FPGA-Based Reconfigurable Hardware
IEEE Design & Test
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
High-level synthesis of distributed logic-memory architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Incorporating compiler feedback into the design of ASIPs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
RTL Synthesis with Physical and Controller Information
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation
ETW '00 Proceedings of the IEEE European Test Workshop
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Fast prototyping of memory models in VHDL for hardware emulation
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
An HOL based framework for design of correct high level synthesizers
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Synchronous Controller Models for Synthesis from Communicating VHDL Processes
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Inductive Verification of Sequential Circuits with a Datapath
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Formal Techniques for Hardware Allocation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A New Methodology for the Design of Asynchronous Digital Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Graph-Theoretic Approach for Register File Based Synthesis
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
High-Level Synthesis with SIMD Units
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
High-level Synthesis of Multi-process Behavioral Descriptions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
High Level Synthesis from Sim-nML Processor Models
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Game-Theoretic Approach for Binding in Behavioral Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
1.3 Parallelism in Structural Fault Testing of Embedded Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Synthesis of low-power selectively-clocked systems from high-level specification
ISSS '96 Proceedings of the 9th international symposium on System synthesis
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Mapping of generalized template matching onto reconfigurable computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Towards a multi-formalism framework for architectural synthesis: the ASAR project
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Range-Compaction Heuristic for Graph Coloring
Journal of Heuristics
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
A compact DSP core with static floating-point unit & its microcode generation
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Modular scheduling of guarded atomic actions
Proceedings of the 41st annual Design Automation Conference
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A novel memory size model for variable-mapping in system level design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Defining an Enhanced RTL Semantics
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
An EFSM-based approach for functional ATPG
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Encyclopedia of Computer Science
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
High-level synthesis: an essential ingredient for designing complex ASICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Scalable interprocedural register allocation for high level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
EFSM Manipulation to Increase High-Level ATPG Effectiveness
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A Formal Verification Method of Scheduling in High-level Synthesis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A Compact DSP Core with Static Floating-Point Arithmetic
Journal of VLSI Signal Processing Systems
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
Optimizing system models for simulation efficiency
Formal methods and models for system design
Dynamic and formal verification of embedded systems: a comparative survey
International Journal of Parallel Programming
Increasing hardware efficiency with multifunction loop accelerators
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Instruction set synthesis with efficient instruction encoding for configurable processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Constrained algorithmic IP design for system-on-chip
Integration, the VLSI Journal
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Multi-objective design space exploration of embedded systems
Journal of Embedded Computing - Low-power Embedded Systems
Multiple voltage synthesis scheme for low power design under timing and resource constraints
Integrated Computer-Aided Engineering
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Register-Transfer Level Transformations for Low-Power Data-Paths
Integrated Computer-Aided Engineering
Using Transport Triggered Architectures for Embedded Processor Design
Integrated Computer-Aided Engineering
Partitioning of Hardware-Software Embedded Systems: A Metrics-based Approach
Integrated Computer-Aided Engineering
Hardware/Software Co-Design Methodology for Design of Embedded Systems
Integrated Computer-Aided Engineering
Efficient design methods for embedded communication systems
EURASIP Journal on Embedded Systems
A hardware/software partitioning algorithm based on artificial immune principles
Applied Soft Computing
Exploiting hierarchy and structure to efficiently solve graph coloring as SAT
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A design flow dedicated to multi-mode architectures for DSP applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design flow instantiation for run-time reconfigurable systems: a case study
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Automated formal verification of scheduling with speculative code motions
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Exploring power reduction options for a single-chip multiprocessor through system-level modeling
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP)
Proceedings of the 45th annual Design Automation Conference
Automatic architecture refinement techniques for customizing processing elements
Proceedings of the 45th annual Design Automation Conference
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
A low-power scheduling tool for system on a chip designs
WSEAS Transactions on Circuits and Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Variation-aware resource sharing and binding in behavioral synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Function Call Optimization for Efficient Behavioral Synthesis
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Behavioral Synthesis Method with Special Functional Units
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A New Datapath Merging Method for Reconfigurable System
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
An interactive design environment for C-based high-level synthesis of RTL processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Scheduling with soft constraints
Proceedings of the 2009 International Conference on Computer-Aided Design
Formal Verification for High-Assurance Behavioral Synthesis
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Using genetic programming and high level synthesis to design optimized datapath
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Data path refinement algorithm in high-level synthesis based on dynamic programming
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
High-level synthesis for the design of FPGA-based signal processing systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Translation validation of high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finding the best compromise in compiling compound loops to Verilog
Journal of Systems Architecture: the EUROMICRO Journal
Logic and high level synthesis for communication protocols
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
RTOS-aware refinement for TLM2.0-based HW/SW designs
Proceedings of the Conference on Design, Automation and Test in Europe
Coordinated resource optimization in behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing equivalence checking for behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Pipelining-based tradeoffs for hardware/software codesign of multimedia systems
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
High-level synthesis for designing multimode architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Code transformations for embedded reconfigurable computing architectures
GTTSE'09 Proceedings of the 3rd international summer school conference on Generative and transformational techniques in software engineering III
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Register pressure aware scheduling for high level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Equivalence checking of scheduling with speculative code transformations in high-level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
On-chip dynamic signal sequence slicing for efficient post-silicon debugging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Design methodology for multifunction vehicle bus devices
ICOSSE'06 Proceedings of the 5th WSEAS international conference on System science and simulation in engineering
A game theoretic approach for power optimization during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate area and delay estimation from RTL descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs
Journal of Electronic Testing: Theory and Applications
Stochastic communication for application-specific Networks-on-Chip
The Journal of Supercomputing
Keynote speech: testing methodologies for embedded systems and systems-on-chip
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Symbolic system level reliability analysis
Proceedings of the International Conference on Computer-Aided Design
Post-silicon debugging targeting electrical errors with patchable controllers (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Proving correctness of regular expression accelerators
Proceedings of the 49th Annual Design Automation Conference
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Anytime algorithms for biobjective heuristic search
AI'12 Proceedings of the 25th Australasian joint conference on Advances in Artificial Intelligence
Translation validation of scheduling in high level synthesis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
A heuristic scheduler for port-constrained floating-point pipelines
International Journal of Reconfigurable Computing
Profit maximization through process variation aware high level synthesis with speed binning
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-pumping for resource reduction in FPGA high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Architecture customization of on-chip reconfigurable accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
A direct method for optimal VLSI realization of deeply nested n-D loop problems
Microprocessors & Microsystems
The benefits of using variable-length pipelined operations in high-level synthesis
ACM Transactions on Embedded Computing Systems (TECS)
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