High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Hardware/software partitioning and minimizing memory interface traffic
EURO-DAC '94 Proceedings of the conference on European design automation
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clustering for improved system-level functional partitioning
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Approximation algorithms for NP-hard problems
Approximation algorithms for NP-hard problems
MILP based task mapping for heterogeneous multiprocessor systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Hardware/Software Partitioning using Integer Programming
EDTC '96 Proceedings of the 1996 European conference on Design and Test
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Process Partitioning for Distributed Embedded Systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Towards a Model for Hardware and Software Functional Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A Co-Design Methodology Based on Formal Specification and High-level Estimation
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Configuration-level hardware/software partitioning for real-time embedded systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
CASTLE: an interactive environment for HW-SW Co-Design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Balancing System Level Pipelines with Stage Voltage Scaling
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
International Journal of Computational Science and Engineering
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In the last years, multimedia systems are present in an ever increasing number of applications. A software implementation often can not satisfy system timing constraints. This problem can be solved by adding specific hardware to the system. Lately, it has been developed some design methodologies for this type of hardware/ software systems. Our research group have developed a hardware/software codesign environment named GACSYS (GAC's Codesign System) for designing this type of systems. In this article, we present our Hw/Sw partitioning tool. Main contribution of our tool is the following: it supports process-level pipelining and takes into account system power consumption. Thus, system designer can explore the design space to make new latency, area and power trade-offs.