Flexible timing specification in a VHDL synthesis subset
EURO-DAC '92 Proceedings of the conference on European design automation
Structured design methodology for high-level design
DAC '94 Proceedings of the 31st annual Design Automation Conference
EURO-DAC '94 Proceedings of the conference on European design automation
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Generating several solutions for the scheduling problem in high-level synthesis
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Semi-dynamic scheduling of synchronization-mechanisms
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Formulation and evaluation of scheduling techniques for control flow graphs
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Timing constraint specification and synthesis in behavioral VHDL
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Synthesis of system-level communication by an allocation-based approach
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Equivalent design representations and transformations for interactive scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Protocol selection and interface generation for HW-SW codesign
Readings in hardware/software co-design
Introduction to High-Level Synthesis
IEEE Design & Test
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing
IEEE Transactions on Computers
Combined Formal Post- and Presynthesis Verification in High Level Synthesis
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Partial Scan High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Hardware/Software Partitioning for Telecommunications Systems
COMPSAC '96 Proceedings of the 20th Conference on Computer Software and Applications
Using Transport Triggered Architectures for Embedded Processor Design
Integrated Computer-Aided Engineering
Hardware/Software Co-Design Methodology for Design of Embedded Systems
Integrated Computer-Aided Engineering
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Pipelining-based tradeoffs for hardware/software codesign of multimedia systems
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
A heuristic scheduler for port-constrained floating-point pipelines
International Journal of Reconfigurable Computing
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