Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Optimizations in high level synthesis
Microprocessing and Microprogramming
REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path tradeoffs using MABAL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Industrial extensions to university high level synthesis tools: Making it work in the real world
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Fast and near optimal scheduling in automatic data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental tree height reduction for high level synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level synthesis in a rapid-prototype environment for mechatronic systems
EURO-DAC '92 Proceedings of the conference on European design automation
High-level transformations for minimizing syntactic variances
DAC '93 Proceedings of the 30th international Design Automation Conference
Integrating program transformations in the memory-based synthesis of image and video algorithms
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Sequencer-based data path synthesis of regular iterative algorithms
DAC '94 Proceedings of the 31st annual Design Automation Conference
Incorporating testability considerations in high-level synthesis
Journal of Electronic Testing: Theory and Applications
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Rephasing: a transformation technique for the manipulation of timing constraints
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Partial scan design of register-transfer level circuits
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
A new approach to the multiport memory allocation problem in data path synthesis
Integration, the VLSI Journal
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
High-level synthesis scheduling and allocation using genetic algorithms
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
A scheduling algorithm for multiport memory minimization in datapath synthesis
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Synthesis-for-testability using transformations
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computing lower bounds on functional units before scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Exploiting regularity for low-power design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Enhancing high-level control-flow for improved testability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Data routing: a paradigm for efficient data-path synthesis and code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Concurrent testing in high-level synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Controller and datapath trade-offs in hierarchical RT-level synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
How datapath allocation affects controller delay
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
High-Level VLSI Synthesis
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
An Optimizer for Hardware Synthesis
IEEE Design & Test
IEEE Design & Test
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
High-level synthesis for easy testability
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A method of automatic data path synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Address Generation for array access based on modulus m counters
EURO-DAC '91 Proceedings of the conference on European design automation
PHIDEO: a silicon compiler for high speed algorithms
EURO-DAC '91 Proceedings of the conference on European design automation
A method for area estimation of data-path in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Datapath synthesis using a problem-space genetic algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavioral synthesis with systemC
Proceedings of the conference on Design, automation and test in Europe
AGENDA: an attribute grammar driven enviornment for the design automation of digital systems
Proceedings of the conference on Design, automation and test in Europe
Statistical design space exploration for application-specific unit synthesis
Proceedings of the 38th annual Design Automation Conference
ISSS '00 Proceedings of the 13th international symposium on System synthesis
A fast approach to computing exact solutions to the resource-constrained scheduling problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Continuous and high coverage self-testing of dynamically re-configurable systems
Parallel Computing - Parallel computing in image and video processing
Refinement and Property Checking in High-Level Synthesis using Attribute Grammars
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An SoC architecture and its design methodology using unifunctional heterogeneous processor array
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Software thread integration for embedded system display applications
ACM Transactions on Embedded Computing Systems (TECS)
Design space exploration using time and resource duality with the ant colony optimization
Proceedings of the 43rd annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Validating High-Level Synthesis
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Non-cycle-accurate sequential equivalence checking
Proceedings of the 46th Annual Design Automation Conference
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Translation validation of high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalence checking for behaviorally synthesized pipelines
Proceedings of the 49th Annual Design Automation Conference
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A systematic approach to classify design-time global scheduling techniques
ACM Computing Surveys (CSUR)
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We survey recent developments in high level synthesis technology for VLSI design. The need for higher-level design automation tools are discussed first. We then describe some basic techniques for various subtasks of high-level synthesis. Techniques that have been proposed in the past few years (since 1994) for various subtasks of high-level synthesis are surveyed. We also survey some new synthesis objectives including testability, power efficiency, and reliability.