CATHEDRAL II—a computer-aided synthesis system for digital signal processing VLSI systems
Computer-Aided Engineering Journal
Memory, control and communications synthesis for scheduled algorithms
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy efficient address assignment through minimized memory row switching
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Architectural Exploration and Optimization for Counter Based Hardware Address Generation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
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The necessary task of Address Generation for RAM and ROM accesses can often result in hardware taking up an appreciable fraction of the area of a data processing IC. Close examination of the address sequences can reveal symmetry which may be exploited to automatically devise small and simple address generators, based on counters. This paper will describe automated techniques used to recognise and develop symmetries in address sequences, and to synthesise the necessary address generation hardware.