Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Address generation for memories containing multiple arrays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Address calculation for retargetable compilation and exploration of instruction-set architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algorithms for address assignment in DSP code generation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power exploration for data dominated video applications
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Analysis and evaluation of address arithmetic capabilities in custom DSP architectures
DAC '97 Proceedings of the 34th annual Design Automation Conference
Advanced compiler design and implementation
Advanced compiler design and implementation
A uniform optimization technique for offset assignment problems
Proceedings of the 11th international symposium on System synthesis
Addressing optimization for loop execution targeting DSP with auto-increment/decrement architecture
Proceedings of the 11th international symposium on System synthesis
High-level address optimization and synthesis techniques for data-transfer-intensive applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of high-level address code transformations for programmable processors
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Register-constrained address computation in DSP programs
Proceedings of the conference on Design, automation and test in Europe
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Optimizing compilers for modern architectures: a dependence-based approach
Optimizing compilers for modern architectures: a dependence-based approach
Code Optimization Techniques for Embedded Processors: Methods, Algorithms, and Tools
Code Optimization Techniques for Embedded Processors: Methods, Algorithms, and Tools
Global array reference allocation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
High-Level Synthesis for Real-Time Digital Signal Processing
High-Level Synthesis for Real-Time Digital Signal Processing
Design Challenges for New Application-Specific Processors
IEEE Design & Test
Deep-Submicron Microprocessor Design Issues
IEEE Micro
Scratchpad memory: design alternative for cache on-chip memory in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Architectural Exploration and Optimization for Counter Based Hardware Address Generation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Address Code and Arithmetic Optimizations for Embedded Systems
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Parallel Media Processors for the Billion-Transistor Era
ICPP '99 Proceedings of the 1999 International Conference on Parallel Processing
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Overcoming the limitations of conventional vector processors
Proceedings of the 30th annual international symposium on Computer architecture
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Address Generation for array access based on modulus m counters
EURO-DAC '91 Proceedings of the conference on European design automation
PHIDEO: a silicon compiler for high speed algorithms
EURO-DAC '91 Proceedings of the conference on European design automation
A loop accelerator for low power embedded VLIW processors
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Control Flow Driven Splitting of Loop Nests at the Source Code Level
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Automatic scenario detection for improved WCET estimation
Proceedings of the 42nd annual Design Automation Conference
Global memory optimisation for embedded systems allowed by code duplication
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Compilers: Principles, Techniques, and Tools (2nd Edition)
Compilers: Principles, Techniques, and Tools (2nd Edition)
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Systematic preprocessing of data dependent constructs for embedded systems
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Signal Assignment Model for the Memory Management of Multidimensional Signal Processing Applications
Journal of Signal Processing Systems
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Nowadays embedded systems are growing at an impressive rate and provide more and more sophisticated applications characterized by having a complex array index manipulation and a large number of data accesses. Those applications require high performance specific computation that general purpose processors can not deliver at a reasonable energy consumption. Very long instruction word architectures seem a good solution providing enough computational performance at low power with the required programmability to speed up the time to market. Those architectures rely on compiler effort to exploit the available instruction and data parallelism to keep the data path busy all the time. With the density of transistors doubling each 18 months, more and more sophisticated architectures with a high number of computational resources running in parallel are emerging. With this increasing parallel computation, the access to data is becoming the main bottleneck that limits the available parallelism. To alleviate this problem, in current embedded architectures, a special unit works in parallel with the main computing elements to ensure efficient feed and storage of the data: the address generator unit, which comes in many flavors. Future architectures will have to deal with enormous memory bandwidth in distributed memories and the development of address generators units will be crucial for effective next generation of embedded processors where global trade-offs between reaction-time, bandwidth, energy and area must be achieved. This paper provides a survey of methods and techniques that optimize the address generation process for embedded systems, explaining current research trends and needs for future.