Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Resource constrained dataflow retiming heuristics for VLIW ASIPs
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Heuristic tradeoffs between latency and energy consumption in register assignment
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Lower bound on latency for VLIW ASIP datapaths
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Cluster assignment for high-performance embedded VLIW processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective
IEEE Transactions on Software Engineering
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
CRISP: A Template for Reconfigurable Instruction Set Processors
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Symbolic Binding for Clustered VLIW ASIPs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
L0 buffer energy optimization through scheduling and exploration
Proceedings of the 2004 ACM symposium on Applied computing
Instruction buffering exploration for low energy VLIWs with instruction clusters
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction buffering exploration for low energy embedded processors
Journal of Embedded Computing - Low-power Embedded Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Joint Source-Channel Decoding ASIP Architecture for Sensor Networks
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Playing the trade-off game: Architecture exploration using Coffeee
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimizing scheduling and intercluster connection for application-specific DSP processors
IEEE Transactions on Signal Processing
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
Microprocessors & Microsystems
| Hi-index | 0.00 |
Embedded systems form a market that is already larger and growing more rapidly than that of general-purpose computers. In fact, real-time multimedia and signal processing embedded applications currently account for over 90% of all computer cycles. This article discusses challenges in developing retargetable compilers and synthesis tools for application-specific processor cores targeted at embedded portable digital communications and multimedia systems