Playing the trade-off game: Architecture exploration using Coffeee

  • Authors:

  • Praveen Raghavan;Murali Jayapala;Andy Lambrechts;Javed Absar;Francky Catthoor

  • Affiliations:

  • IMEC vzw, Belgium and ESAT, Katholieke Universiteit Leuven, Belgium;IMEC vzw, Belgium;IMEC vzw, Belgium and ESAT, Katholieke Universiteit Leuven, Belgium;ST Microelectronics, Bristol, UK;IMEC vzw, Belgium and ESAT, Katholieke Universiteit Leuven, Belgium

  • Venue:
  • ACM Transactions on Design Automation of Electronic Systems (TODAES)
  • Year:
  • 2009

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Abstract

Modern mobile devices need to be extremely energy efficient. Due to the growing complexity of these devices, energy-aware design exploration has become increasingly important. Current exploration tools often do not support energy estimation, or require the design to be very detailed before estimation is possible. It is important to get early feedback on both performance and energy consumption during all phases of the design and at higher abstraction levels. This article presents a unified optimization and exploration framework to explore source-level transformation to processor architecture design space. The proposed retargetable compiler and simulator framework can map applications to a range of processors and memory configurations, simulate, and report detailed performance and energy estimates. An accurate and consistent energy modeling approach is introduced which can estimate the energy consumption of processor and memories at a component level, which can help to guide the design process. Fast energy-aware architecture exploration is illustrated by modeling both state-of-the-art processors as well as other architectures. Various design trade-offs are also illustrated on different academic as well as industrial benchmarks from both the wireless communication and multimedia domain. We also illustrate a design space exploration on different applications and show that there is large trade-off space between application performance, energy consumption, and area. We show that the proposed framework is consistent, accurate, and covers a large design space including various novel low-power extensions in a unified framework.