Introduction to programmable active memories
Systolic array processors
Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
Design and implementation of the “Tiny RISC” microprocessor
Microprocessors & Microsystems
Practical programming in Tcl and Tk (2nd ed.)
Practical programming in Tcl and Tk (2nd ed.)
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
Configurable computing: the catalyst for high-performance architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The RAW benchmark suite: computation structures for general purpose computing
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Automated target recognition on SPLASH 2
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
High-performance automatic target recognition through data-specific VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HW / SW partitioning approach for reconfigurable system design
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Processor Array Synthesis from Shift-Variant Deep Nested Do Loops
The Journal of Supercomputing
Compilation Approach for Coarse-Grained Reconfigurable Architectures
IEEE Design & Test
A Novel Predication Scheme for a SIMD System-on-Chip
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
CODACS Project: A Demand-Data Driven Reconfigurable Architecture (Research Note)
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note)
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Field-Programmable Custom Computing Machines - A Taxonomy -
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Quantitative Understanding of the Performance of Reconfigurable Coprocessors
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An algorithm for mapping loops onto coarse-grained reconfigurable architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
A fast parallel reed-solomon decoder on a reconfigurable architecture
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Automatic compilation to a coarse-grained reconfigurable system-opn-chip
ACM Transactions on Embedded Computing Systems (TECS)
A scalable wide-issue clustered VLIW with a reconfigurable interconnect
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Performance of reconfigurable architectures for image-processing applications
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 3
MaRS: a macro-pipelined reconfigurable system
Proceedings of the 1st conference on Computing frontiers
Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
IEEE Transactions on Computers
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE-Compliant IDCT on FPGA-Augmented TriMedia
Journal of VLSI Signal Processing Systems
An Instruction-Level Distributed Processor for Symmetric-Key Cryptography
IEEE Transactions on Parallel and Distributed Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
CODACS Prototype: A Platform-Processor for CHIARA Programs
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 13 - Volume 14
Architecture Exploration for a Reconfigurable Architecture Template
IEEE Design & Test
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems
Proceedings of the 32nd annual international symposium on Computer Architecture
Designing real-time H.264 decoders with dataflow architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Physical resource binding for a Coarse-Grain reconfigurable array using evolutionary algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Interactive ray tracing on reconfigurable SIMD MorphoSys
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
IEEE-compliant IDCT on FPGA-augmented TriMedia
Journal of VLSI Signal Processing Systems
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
System-level scheduling on instruction cell based reconfigurable systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A parallel configuration model for reducing the run-time reconfiguration overhead
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Optimizing compiler for shared-memory multiple SIMD architecture
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Reconfigurable Coprocessor for Multimedia Application Domain
Journal of VLSI Signal Processing Systems
Extracting and improving microarchitecture performance on reconfigurable architectures
International Journal of Parallel Programming - Special issue: The next generation software program
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
The Journal of Supercomputing
Proceedings of the 2006 international symposium on Low power electronics and design
Journal of Experimental Algorithmics (JEA)
A synthesizable datapath-oriented embedded FPGA fabric
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms
Microprocessors & Microsystems
Compiler assisted architectural exploration for coarse grained reconfigurable arrays
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The Journal of Supercomputing
A unified evaluation framework for coarse grained reconfigurable array architectures
Proceedings of the 4th international conference on Computing frontiers
Massively parallel processing on a chip
Proceedings of the 4th international conference on Computing frontiers
Speedups in embedded systems with a high-performance coprocessor datapath
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
An Integrated Memory Array Processor for Embedded Image Recognition Systems
IEEE Transactions on Computers
A dynamically adaptive DSP for heterogeneous reconfigurable platforms
Proceedings of the conference on Design, automation and test in Europe
A dynamically adaptive DSP for heterogeneous reconfigurable platforms
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Static scheduling techniques for dependent tasks on dynamically reconfigurable devices
Journal of Systems Architecture: the EUROMICRO Journal
RoSA: a reconfigurable stream-based architecture
Proceedings of the 20th annual conference on Integrated circuits and systems design
FPGA-based configurable systolic architecture for window-based image processing
EURASIP Journal on Applied Signal Processing
3D-softchip: a novel architecture for next-generation adaptive computing systems
EURASIP Journal on Applied Signal Processing
Improving instruction level parallelism through reconfigurable units in superscalar processors
ACM SIGARCH Computer Architecture News - Special issue on the 2006 reconfigurable and adaptive architecture workshop
An energy-efficient reconfigurable baseband processor for wireless communications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Optimized mapping for enchancing the operation parallelism in coarse-grained reconfigurable arrays
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
Accelerated AES implementations via generalized instruction set extensions
Journal of Computer Security - The Third IEEE International Symposium on Security in Networks and Distributed Systems
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
Journal of Signal Processing Systems
Journal of Systems Architecture: the EUROMICRO Journal
CUBA: an architecture for efficient CPU/co-processor data communication
Proceedings of the 22nd annual international conference on Supercomputing
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
The reconfigurable instruction cell array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Speedups and energy reductions from mapping DSP applications on an embedded reconfigurable system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coarse-grained array based baseband processor for 100Mbps+ software defined radio
Proceedings of the conference on Design, automation and test in Europe
High-level modelling and exploration of coarse-grained re-configurable architectures
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Hybrid Pipeline Structure for Self-Organizing Learning Array
ISNN '07 Proceedings of the 4th international symposium on Neural Networks: Part II--Advances in Neural Networks
ARISE Machines: Extending Processors with Hybrid Accelerators
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Compiling custom instructions onto expression-grained reconfigurable architectures
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
A holistic approach for tightly coupled reconfigurable parallel processors
Microprocessors & Microsystems
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
A framework for low energy data management in reconfigurable multi-context architectures
Journal of Systems Architecture: the EUROMICRO Journal
SPR: an architecture-adaptive CGRA mapping tool
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Mapping method for dynamically reconfigurable architecture
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Resource aware mapping on coarse grained reconfigurable arrays
Microprocessors & Microsystems
A design flow for architecture exploration and implementation of partially reconfigurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEICE - Transactions on Information and Systems
Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration
IEICE - Transactions on Information and Systems
Playing the trade-off game: Architecture exploration using Coffeee
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic context management for low power coarse-grained reconfigurable architecture
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays
The Journal of Supercomputing
Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor
Microprocessors & Microsystems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
An Application Development Framework for ARISE Reconfigurable Processors
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Integration, the VLSI Journal
BRICK: a multi-context expression grained reconfigurable architecture
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems
Proceedings of the 46th Annual Design Automation Conference
EURASIP Journal on Embedded Systems
FleXilicon architecture and its VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An asymmetric distributed shared memory model for heterogeneous parallel systems
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
ACM Transactions on Architecture and Code Optimization (TACO)
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Data pipeline optimization for shared memory multiple-SIMD architecture
LCPC'06 Proceedings of the 19th international conference on Languages and compilers for parallel computing
Architectural exploration of the ADRES coarse-grained reconfigurable array
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
MORA: a new coarse-grain reconfigurable array for high throughput multimedia processing
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
On the implementation of virtual array using configuration plane
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Architecture enhancements for the ADRES coarse-grained reconfigurable array
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
HiPC'08 Proceedings of the 15th international conference on High performance computing
Design on operator-based reconfigurable hardware architecture and cell circuit
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures
Journal of Signal Processing Systems
Dynamic context compression for low-power coarse-grained reconfigurable architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selecting profitable custom instructions for reconfigurable processors
Journal of Systems Architecture: the EUROMICRO Journal
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors
Journal of Signal Processing Systems
Proceedings of the Conference on Design, Automation and Test in Europe
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Modeling and evaluation of ring-based interconnects for Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Binary acceleration using coarse-grained reconfigurable architecture
ACM SIGARCH Computer Architecture News
PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model
International Journal of High Performance Systems Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Enhancing the performance of symmetric-key cryptography via instruction set extensions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient specialization of functional units in a coarse-grained reconfigurable array
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power reconfiguration technique for coarse-grained reconfigurable architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rapid functional modelling and simulation of coarse grained reconfigurable array architectures
Journal of Systems Architecture: the EUROMICRO Journal
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Partitioning signal processing applications to different granularity reconfigurable logic
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Speedups from executing critical software segments to coarse-grain reconfigurable logic
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
Performance improvements of microprocessor platforms with a coarse-grained reconfigurable data-path
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
High performance programmable FPGA overlay for digital signal processing
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
High performance and area efficient flexible DSP datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The ARISE approach for extending embedded processors with arbitrary hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Improving performance of nested loops on reconfigurable array processors
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Memory-centric communication architecture for reconfigurable computing
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
A high efficient on-chip interconnection network in SIMD CMPs
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Memory-Aware application mapping on coarse-grained reconfigurable arrays
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
2-D discrete cosine transform (DCT) on meshes with hierarchical control modes
IbPRIA'05 Proceedings of the Second Iberian conference on Pattern Recognition and Image Analysis - Volume Part I
Memory-based computing for performance and energy improvement in multicore architectures
Proceedings of the great lakes symposium on VLSI
Exploiting both pipelining and data parallelism with SIMD reconfigurable architecture
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
A dynamic component model for cyber physical systems
Proceedings of the 15th ACM SIGSOFT symposium on Component Based Software Engineering
A coarse-grained reconfigurable architecture with compilation for high performance
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems
Journal of Signal Processing Systems
Performance optimization of embedded applications in a hybrid reconfigurable platform
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
QUKU: A dual-layer reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
ACM Transactions on Embedded Computing Systems (TECS)
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs
Proceedings of the Conference on Design, Automation and Test in Europe
Compiling control-intensive loops for CGRAs with state-based full predication
Proceedings of the Conference on Design, Automation and Test in Europe
GPU-CC: a reconfigurable GPU architecture with communicating cores
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A just-in-time customizable processor
Proceedings of the International Conference on Computer-Aided Design
A hyperscalar dual-core architecture for embedded systems
Microprocessors & Microsystems
Integration, the VLSI Journal
Configurable range memory for effective data reuse on programmable accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms
Journal of Real-Time Image Processing
Design of the coarse-grained reconfigurable architecture DART with on-line error detection
Microprocessors & Microsystems
Hi-index | 14.99 |
This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems.