IEEE Transactions on Computers
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
IEEE Transactions on Computers
Scalable Processor Instruction Set Extension
IEEE Design & Test
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays
The Journal of Supercomputing
PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model
International Journal of High Performance Systems Architecture
Efficient resource sharing architecture for multistandard communication system
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
Hi-index | 0.00 |
This paper presents performance improvements and energy savings from mapping real-world benchmarks on an embedded single-chip platform that includes coarse-grained reconfigurable logic with a micro-processor. The reconfigurable hardware is a 2-D array of processing elements connected with a mesh-like network. Analytical results derived from mapping seven real-life digital signal processing applications, with the aid of an automated design flow, on six different instances of the system architecture are presented. Significant overall application speedups relative to an all-software solution, ranging from 1.81 to 3.99 are reported being close to theoretical speedup bounds. Additionally, the energy savings range from 43% to 71%. Finally, a comparison with a system coupling a micro-processor with a very long instruction word core shows that the micro-processor/coarse-grained reconfigurable array platform is more efficient in terms of performance and energy consumption.