BISON: a fast hybrid procedure for exactly solving the one-dimensional bin packing problem
Computers and Operations Research
New heuristics for one-dimensional bin-packing
Computers and Operations Research
Configuration relocation and defragmentation for run-time reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Introducing ReConfigME: An Operating System for Reconfigurable Computing
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Chip-Based Reconfigurable Task Management
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Run-time support for dynamically reconfigurable computing systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
A Hybrid Improvement Heuristic for the One-Dimensional Bin Packing Problem
Journal of Heuristics
Online Scheduling for Block-Partitioned Reconfigurable Devices
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Hard Real-time Computing Systems: Predictable Scheduling Algorithms And Applications (Real-Time Systems Series)
Packet Routing in Dynamically Changing Networks on Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
A Reconfiguration Manager for Dynamically Reconfigurable Hardware
IEEE Design & Test
A dynamically reconfigurable packet-switched network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Weight annealing heuristics for solving bin packing and other combinatorial optimization problems: concepts, algorithms, and computational results
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
ACM Transactions on Embedded Computing Systems (TECS)
Speedups and energy reductions from mapping DSP applications on an embedded reconfigurable system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Organization of computer systems: the fixed plus variable structure computer
IRE-AIEE-ACM '60 (Western) Papers presented at the May 3-5, 1960, western joint IRE-AIEE-ACM computer conference
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs
Microprocessors & Microsystems
Microprocessors & Microsystems
A run-time partitioning algorithm for RTOS on reconfigurable hardware
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
A reconfigurable 8 GOP ASIC architecture for high-speed data communications
IEEE Journal on Selected Areas in Communications
Real-Time Neural Network Inversion on the SRC-6e Reconfigurable Computer
IEEE Transactions on Neural Networks
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Reconfigurable computing is a promising technique for real time computing-intensive embedded applications. In this paper, we propose a novel hardware task model and an optimal 2D surface partitioning strategy for managing a partially run time reconfigurable hardware resource. A mesh network-on-chip is designed to be used as the communication environment for the hardware tasks. An offline design flow is proposed for generating the bit-stream and finally, an online real time operating system scheduler that supports true hardware multitasking is presented. The proposed components form the necessary building blocks of a complete reconfigurable computing platform suitable for real time computing-intensive embedded applications.