HGA: a hardware-based genetic algorithm
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
Practical Genetic Algorithms with CD-ROM
Practical Genetic Algorithms with CD-ROM
Creating an adaptive embedded system by applying multi-agent techniques to reconfigurable hardware
Future Generation Computer Systems - Special issue: Computational science of lattice Boltzmann modelling
Concurrency and Computation: Practice & Experience
Hardware implementation of a novel genetic algorithm
Neurocomputing
Genetic Algorithm that can Dynamically Change Number of Individuals and Accuracy
FBIT '07 Proceedings of the 2007 Frontiers in the Convergence of Bioscience and Information Technologies
A New Leading Crossover Operator for Function Optimization
CSIE '09 Proceedings of the 2009 WRI World Congress on Computer Science and Information Engineering - Volume 04
High-speed FPGA-based implementations of a genetic algorithm
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine
IEEE Transactions on Evolutionary Computation
FPGA Based Engines for Genetic and Memetic Algorithms
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
A deterministic annular crossover genetic algorithm optimisation for the unit commitment problem
Expert Systems with Applications: An International Journal
Compact Genetic Algorithms using belief vectors
Applied Soft Computing
Challenges of evolvable hardware: past, present and the path to a promising future
Genetic Programming and Evolvable Machines
Genetic Programming and Evolvable Machines
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
A genetic approach to standard cell placement using meta-genetic parameter optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this article a new architecture for hardware implementation of genetic algorithm in reconfigurable embedded systems is presented. The main idea is based on the efficient use of a genetic algorithm's crossover operator to enhance the speed of algorithm to reach an optimal solution. In this article a new crossover called DSO and also two new architectures for implementation of crossover operators are introduced to provide suitable solutions for solving the problems related to fitness function of the genetic algorithm. At first, some optimum operators are selected and then utilized in a new parallel architecture to increase the speed and accuracy of algorithm convergence. Finally, based on reusability of existing resources, the main idea of the article is introduced to improve the performance of the algorithm and finding the optimal solution. The properties of FPGAs such as flexibility and parallelism help this purpose.