Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
HGA: a hardware-based genetic algorithm
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Practical Unix and Internet security (2nd ed.)
Practical Unix and Internet security (2nd ed.)
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Evolutionary Electronics: Automatic Design of Electronic Circuits and Systems by Genetic Algorithms
Evolutionary Electronics: Automatic Design of Electronic Circuits and Systems by Genetic Algorithms
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Evolvable Hardware for Space Applications
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Genetic Algorithms for the Traveling Salesman Problem
Proceedings of the 1st International Conference on Genetic Algorithms
On Random Numbers And The Performance Of Genetic Algorithms
GECCO '02 Proceedings of the Genetic and Evolutionary Computation Conference
Evolutionary Search for Minimal Elements in Partially Ordered Finite Sets
EP '98 Proceedings of the 7th International Conference on Evolutionary Programming VII
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
PACT XPP—A Self-Reconfigurable Data Processing Architecture
The Journal of Supercomputing
Practical Genetic Algorithms with CD-ROM
Practical Genetic Algorithms with CD-ROM
High level techniques for leakage power estimation and optimization in vlsi asics
High level techniques for leakage power estimation and optimization in vlsi asics
Massively Parallel Hardware Architecture for Genetic Algorithms
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications
AHS '08 Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems
Optimization of single variable functions using complete hardware evolution
Applied Soft Computing
An FPGA implementation of the SMG-SLAM algorithm
Microprocessors & Microsystems
Designing digital circuits for FPGAs using parallel genetic algorithms (WIP)
Proceedings of the 2012 Symposium on Theory of Modeling and Simulation - DEVS Integrative M&S Symposium
A hybrid evolutionary approach to segmentation of non-stationary signals
Digital Signal Processing
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Hardware implementation of genetic algorithms (GAs) is gaining importance because of their proven effectiveness as optimization engines for real-time applications (e.g., evolvable hardware). Earlier hardware implementations suffer from major drawbacks such as absence of GA parameter programmability, rigid predefined system architecture, and lack of support for multiple fitness functions. In this paper, we report the design of an IP core that implements a general-purpose GA engine that addresses these problems. Specifically, the proposed GA IP core can be customized in terms of the population size, number of generations, crossover and mutation rates, random number generator seed, and the fitness function. It has been successfully synthesized and verified on a Xilinx Virtex II Pro Field programmable gate arrays device (xc2vp30-7ff896) with only 13% logic slice utilization, 1% block memory utilization for GA memory, and a clock speed of 50MHz. The GA core has been used as a search engine for realtime adaptive healing but can be tailored to any given application by interfacing with the appropriate application-specific fitness evaluation module as well as the required storage memory and by programming the values of the desired GA parameters. The core is soft in nature i.e., a gate-level netlist is provided which can be readily integrated with the user's system. The performance of the GA core was tested using standard optimization test functions. In the hardware experiments, the proposed core either found the globally optimum solution or found a solution that was within 3.7% of the value of the globally optimal solution. The experimental test setup including the GA core achieved a speedup of around 5.16× over an analogous software implementation.