EURO-DAC '92 Proceedings of the conference on European design automation
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
A verification technique for gated clock
DAC '93 Proceedings of the 30th international Design Automation Conference
Sequential synthesis for table look up programmable gate arrays
DAC '93 Proceedings of the 30th international Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Minimum length synchronizing sequences of finite state machine
DAC '93 Proceedings of the 30th international Design Automation Conference
Sequential circuit delay optimization using global path delays
DAC '93 Proceedings of the 30th international Design Automation Conference
Resynthesis of multi-phase pipelines
DAC '93 Proceedings of the 30th international Design Automation Conference
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A symbolic method to reduce power consumption of circuits containing false paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level synthesis for safe replaceability
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Design of heterogeneous ICs for mobile and personal communication systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Provably correct high-level timing analysis without path sensitization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Clock period optimization during resource sharing and assignment
DAC '94 Proceedings of the 31st annual Design Automation Conference
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance optimization using exact sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Automatic verification of pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
EURO-DAC '94 Proceedings of the conference on European design automation
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Functional multiple-output decomposition: theory and an implicit algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On test set preservation of retimed circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic clause analysis for delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Externally hazard-free implementations of asynchronous circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Transformation and synthesis of FSMs for low-power gated-clock implementation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Exploiting power-up delay for sequential optimization
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Logic decomposition during technology mapping
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast functional simulation using branching programs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Boolean techniques for low power driven re-synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Two-level logic minimization for low power
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A delay model for logic synthesis of continuously-sized networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Cost-free scan: a low-overhead scan path design methodology
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Low power realization of finite state machines—a decomposition approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Multi-level logic optimization for low power using local logic transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Using complete-1-distinguishability for FSM equivalence checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Latch optimization in circuits generated from high-level descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Mapping statechart models onto an FPGA-based ASIP architecture
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Automatic structuring and optimization of hierarchical designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Symbolic computation of logic implications for technology-dependent low-power synthesis
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
How datapath allocation affects controller delay
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Scheduling a minimum dependence in FSMs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A simple algorithm for fanout optimization using high-performance buffer libraries
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Quick conservative causality analysis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
A symbolic algorithm for low-power sequential synthesis
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Re-mapping for low power under tight timing constraints
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Efficient latch optimization using exclusive sets
DAC '97 Proceedings of the 34th annual Design Automation Conference
Telescopic units: increasing the average throughput of pipelined designs by adaptive latency control
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimizing designs containing black boxes
DAC '97 Proceedings of the 34th annual Design Automation Conference
Linear sifting of decision diagrams
DAC '97 Proceedings of the 34th annual Design Automation Conference
A test synthesis approach to reducing BALLAST DFT overhead
DAC '97 Proceedings of the 34th annual Design Automation Conference
A hybrid algorithm for test point selection for scan-based BIST
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hierarchical test generation and design for testability of ASPPs and ASIPs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
Generalized matching from theory to application
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast power estimation for deterministic input streams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Don't care-based BDD minimization for embedded software
DAC '98 Proceedings of the 35th annual Design Automation Conference
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Node sampling: a robust RTL power modeling approach
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fanout optimization under a submicron transistor-level delay model
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal clock period FPGA technology mapping for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power reduction and power-delay trade-offs using logic transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Automatic compositional minimization in CTL model checking
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Performance optimization of sequential circuits by eliminating retiming bottlenecks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Exploiting multi-cycle false paths in the performance optimization of sequential circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Performance-driven scheduling with bit-level chaining
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting
IEEE Transactions on Computers
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient power co-estimation techniques for system-on-chip design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Power and delay reduction via simultaneous logic and placement optimization in FPGAs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Built-in-self-test with an alternating output
Proceedings of the conference on Design, automation and test in Europe
Technology mapping for minimizing gate and routing area
Proceedings of the conference on Design, automation and test in Europe
On mixture density and maximum likelihood power estimation via expectation-maximization
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Using complete-1-distinguishability for FSM equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimizing designs containing black boxes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TAO: regular expression-based register-transfer level testability analysis and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Logic Synthesis and Verification
Hardware-software codesign of embedded systems
Readings in hardware/software co-design
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
An exact gate assignment algorithm for tree circuits under rise and fall delays
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Compatible observability don't cares revisited
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Cosimulation-based power estimation for system-on-chip design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
Testability Implications of Performance-Driven Logic Synthesis
IEEE Design & Test
Fast Power Estimation of Large Circuits
IEEE Design & Test
A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures
IEEE Transactions on Computers
Synthesis and placement flow for gain-based programmable regular fabrics
Proceedings of the 2003 international symposium on Physical design
Evolutionary Systems Applied to the Synthesis of a CPU Controller
SEAL'98 Selected papers from the Second Asia-Pacific Conference on Simulated Evolution and Learning on Simulated Evolution and Learning
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Sequential optimization in the absence of global reset
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Gain-based technology mapping for discrete-size cell libraries
Proceedings of the 40th annual Design Automation Conference
Software transformations for sequential test generation
ATS '95 Proceedings of the 4th Asian Test Symposium
Optimised state assignment for asynchronous circuit synthesis
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Optimization of combinational and sequential logic circuits for low power using precomputation
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Modeling and optimization of hierarchical synchronous circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Decomposition of logic functions for minimum transition activity
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Design for Testability of Gated-Clock FSMs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Improving the Accuracy of Support-Set Finding Method for Power Estimation of Combinational Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Optimum retiming of large sequential circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Functional clock schedule optimization
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
9.3 Improving Path Delay Fault Testability by Path Removal
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Reducing Test Application Time in High-Level Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Fast Test Generation for Circuits with RTL and Gate-Level Views
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Efficient Identification of Non-Robustly Untestable Path Delay Faults
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ILP-based optimization of sequential circuits for low power
Proceedings of the 2003 international symposium on Low power electronics and design
On-Line Monitor Design of Finite-State Machines
Journal of Electronic Testing: Theory and Applications
A case study in computer-aided codesign of embedded controllers
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Managing Don't Cares in Boolean Satisfiability
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Cycle-Accurate Energy Measurement and Characterization of FPGAs
Analog Integrated Circuits and Signal Processing
An effective and efficient ATPG-based combinational equivalence checker
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Multimode power modeling and maximum-likelihood estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Designing logic circuits for probabilistic computation in the presence of noise
Proceedings of the 42nd annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
An Improved Approach for AlternativeWires Identi.cation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Debugging sequential circuits using Boolean satisfiability
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Logic verification based on diagnosis techniques
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An automatic interconnection rectification technique for SoC design integration
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Test generation for combinational quantum cellular automata (QCA) circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Test sequence generation for controller verification and test with high coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EPspectra: a formal toolkit for developing DSP software applications
Theory and Practice of Logic Programming
Synthesis of irregular combinational functions with large don't care sets
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Accurate timing analysis using SAT and pattern-dependent delay models
Proceedings of the conference on Design, automation and test in Europe
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Automatic test generation for combinational threshold logic networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A test generation framework for quantum cellular automata circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A generalization of a fast RNS conversion for a new 4-modulus base
IEEE Transactions on Circuits and Systems II: Express Briefs
Multi-level clustering for clock skew optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Integration, the VLSI Journal
A SVD-based fragile watermarking scheme for image authentication
IWDW'02 Proceedings of the 1st international conference on Digital watermarking
Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine
IEEE Transactions on Evolutionary Computation
NanoV: nanowire-based VLSI design
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Synthesis-for-testability watermarking for field authenticatioil of VLSI intellectual property
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Sequential logic rectifications with approximate SPFDs
Proceedings of the Conference on Design, Automation and Test in Europe
A practical method for multi-domain clock skew optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Performance-driven synthesis in controller-datapath systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SEC'13 Proceedings of the 22nd USENIX conference on Security
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