Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Constructive Analysis of Cyclic Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Efficient latch optimization using exclusive sets
DAC '97 Proceedings of the 34th annual Design Automation Conference
Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions
DAC '98 Proceedings of the 35th annual Design Automation Conference
Performance driven resynthesis by exploiting retiming-induced state register equivalence
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal Methods in System Design
Formal Methods in Designing Embedded Systems—the SACRES Experience
Formal Methods in System Design
Software synthesis from synchronous specifications using logic simulation techniques
Proceedings of the 39th annual Design Automation Conference
Compositional Verification of Synchronous Networks
FTRTFT '00 Proceedings of the 6th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Optimizing Symbolic Model Checking for Constraint-Rich Models
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Introducing Mutual Exclusion in Esterel
PSI '99 Proceedings of the Third International Andrei Ershov Memorial Conference on Perspectives of System Informatics
EPspectra: a formal toolkit for developing DSP software applications
Theory and Practice of Logic Programming
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Dependent-latch identification in reachable state space
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Applying Techniques of Asynchronous Concurrency to Synchronous Languages
Fundamenta Informaticae
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In a gate-level description of a finite state machine (\fsm), there is a tradeoff between the number of latches and the size of the logic implementing the next-state and output functions. Typically, an initial implementation is generated via explicit state assignment or translation from a high-level language, and the tradeoff is subsequently only lightly explored. We efficiently explore good latch/logic tradeoffs for large designs generated from high-level specifications. We reduce the number of latches while controlling the logic size. We demonstrate the efficacy of our techniques on some large industrial examples.