Statecharts: A visual formalism for complex systems
Science of Computer Programming
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Latch optimization in circuits generated from high-level descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A system for compiling and debugging structured data processing controllers
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Controller optimization for protocol intensive applications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Efficient latch optimization using exclusive sets
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and synthesis of array structured telecommunication processing applications
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interface synthesis: a vertical slice from digital logic to software components
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-level synthesis with distributed controller for fast timing closure
Proceedings of the International Conference on Computer-Aided Design
Critical-path-aware high-level synthesis with distributed controller for fast timing closure
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper describes methods for partitioning and optimizing controllers described by hierarchical high-level descriptions. The methods utilize the structure of the high-level description, provide flexible exploration of the trade-off between combinational logic and registers to reduce implementation cost, and allow the designer to control the synthesis process. Results are presented using industrial examples.