Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions
DAC '98 Proceedings of the 35th annual Design Automation Conference
A method of distributed controller design for RTL circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A global interconnect reduction technique during high level synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Performance-driven synthesis in controller-datapath systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generation of distributed logic-memory architectures through high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unified Incremental Physical-Level and High-Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical-path-aware high-level synthesis with distributed controller for fast timing closure
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Centralized controllers commonly used in high-level synthesis often cause long wires and high load capacitance and that is why critical paths typically occur on paths from controllers to data registers. However, conventional high level synthesis has focused on the delay of datapaths making it difficult to solve the timing closure problem during physical synthesis. This paper presents a hardware architecture with a distributed controller, which makes the timing closure problem much easier. It also presents a novel high-level synthesis flow for synthesizing such hardware through datapath partitioning and controller optimization. According to our experimental results, the proposed approach reduces the controller and interconnect delay by 20.3-27.4% and the entire critical path delay by 6.6~10.3% with 0.2~13.3% area overhead. Even without area overhead, it reduces the critical path delay by 5.8~10%.