Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions
DAC '98 Proceedings of the 35th annual Design Automation Conference
A method of distributed controller design for RTL circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimizing Register Binding in FPGAs Using Simulated Annealing
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A global interconnect reduction technique during high level synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Performance-driven synthesis in controller-datapath systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimum clique partition problem with constrained weight for interval graphs
COCOON'06 Proceedings of the 12th annual international conference on Computing and Combinatorics
High-level synthesis with distributed controller for fast timing closure
Proceedings of the International Conference on Computer-Aided Design
The JPEG still picture compression standard
IEEE Transactions on Consumer Electronics
An output encoding problem and a solution technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Procedure for Placement of Standard-Cell VLSI Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generation of distributed logic-memory architectures through high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unified Incremental Physical-Level and High-Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Centralized controllers commonly used in high-level synthesis often require long wires and cause high load capacitance, and that is why critical paths typically occur on paths from controllers to data registers instead of paths from data registers to data registers. However, conventional high-level synthesis has focused on delays within a datapath, making it difficult to solve the timing closure problem during physical synthesis. This article presents hardware architecture with a distributed controller, which makes the timing closure problem much easier. A novel critical-path-aware high-level synthesis flow is also presented for synthesizing such hardware through datapath partitioning, register binding, and controller optimization. We explore the design space related to the number of partitions, which is an important design parameter for target architecture. According to our experiments, the proposed approach reduces the critical path delay excluding FUs by 29.3% and that including FUs by 10.0%, with 2.2% area overhead on average compared to centralized controller architecture.