Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Authors:
Jason Cong;Yiping Fan;Guoling Han;Xun Yang;Zhiru Zhang
Affiliations:
University of California, Los Angeles;University of California, Los Angeles;University of California, Los Angeles;University of California, Los Angeles;University of California, Los Angeles
Venue:
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Year:
2003

Citing 17
Cited 6

An efficient method of computing static single assignment form

POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
3D scheduling: high-level synthesis with floorplanning

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Simultaneous functional-unit binding and floorplanning

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Understanding retiming through maximum average-delay cycles

Proceedings of the 3rd ACM symposium on Parallel algorithms and architectures
Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits

DAC '97 Proceedings of the 34th annual Design Automation Conference
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Timing-driven placement for FPGAs

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
High-level synthesis under multi-cycle interconnect delay

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Integrated retiming and placement for field programmable gate arrays

FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Timing closure based on physical hierarchy

Proceedings of the 2002 international symposium on Physical design
Synthesis and Optimization of Digital Circuits

Synthesis and Optimization of Digital Circuits
Physical planning with retiming

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Behavior-to-placed RTL synthesis with performance-driven placement

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Architecture and synthesis for multi-cycle communication

Proceedings of the 2003 international symposium on Physical design
Layout-driven resource sharing in high-level synthesis

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel global placement with retiming

Proceedings of the 40th annual Design Automation Conference

Architecture-level synthesis for automatic interconnect pipelining

Proceedings of the 41st annual Design Automation Conference
Resource sharing in pipelined CDFG synthesis

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast timing closure by interconnect criticality driven delay relaxation

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design closure driven delay relaxation based on convex cost network flow

Proceedings of the conference on Design, automation and test in Europe
High-level synthesis with distributed controller for fast timing closure

Proceedings of the International Conference on Computer-Aided Design
Critical-path-aware high-level synthesis with distributed controller for fast timing closure

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Multiple clock cycles are needed to cross the global interconnectsfor multi-gigahertz designs in nanometer technologies. Forsynchronous design, this requires the consideration of multi-cycleon-chip communication at the high level. In this paper, we presenta new architectural synthesis system integrated with globalplacement, named MCAS (Multi-Cycle Architectural Synthesis),on top of the recently-proposed Regular Distributed Register(RDR) micro-architecture. The RDR architecture provides aregular synthesis platform for supporting multi-cyclecommunication. Novel architectural synthesis algorithms thatintegrate high-level synthesis with global placement have beendeveloped in MCAS, including scheduling-driven placement anddistributed controller generation, etc. Experimental results showthat our methodology can achieve a clock period improvement of31% and a total latency improvement of 24% on averagecompared to the conventional architectural synthesis flow.