Introduction to algorithms
Sequential circuit delay optimization using global path delays
DAC '93 Proceedings of the 30th international Design Automation Conference
Understanding retiming through maximum average-delay cycles
Proceedings of the 3rd ACM symposium on Parallel algorithms and architectures
Simultaneous depth and area minimization in LUT-based FPGA mapping
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Functional multiple-output decomposition: theory and an implicit algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Technology mapping of sequential circuits for LUT-based FPGAs for performance
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal clock period FPGA technology mapping for sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimal clock period FPGA technology mapping for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
FPGA Synthesis Using Function Decomposition
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Optimal clock period FPGA technology mapping for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A comparing study of technology mapping for FPGA
Proceedings of the conference on Design, automation and test in Europe
Architecture and synthesis for multi-cycle communication
Proceedings of the 2003 international symposium on Physical design
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Bit-level partial evaluation of synchronous circuits
Proceedings of the 2006 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Wave-pipelined intra-chip signaling for on-FPGA communications
Integration, the VLSI Journal
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In this paper, we present a new algorithm, named TurboSYN,for FPGA synthesis with retiming and pipelining to minimizethe clock period for sequential circuits.For a target clockperiod, since pipelining can eliminate all critical I/O paths,but not critical loops, we concentrate on FPGA synthesis toeliminate the critical loops.We combine the combinationalfunctional decomposition technique with retiming to performthe sequential functional decomposition, and incorporate itin the label computation of TurboMap to eliminate allcritical loops.The results show a significant improvementover the state-of-the-art FPGA mapping and resynthesis algorithms(1.7 ~ 2 times reduction on the clock period).Moreover,we develop a novel approach for positive loop detectionwhich leads to over 10 ~ 50 times speedup of the algorithm.As a result, TurboSYN can optimize sequential circuits ofover 10驴 gates and 10{3} flipflops in reasonable time.