FPGA Synthesis Using Function Decomposition

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Partially-dependent functional decomposition with applications in FPGA synthesis and mapping

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays

FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits

DAC '97 Proceedings of the 34th annual Design Automation Conference

Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

FPGA synthesis for minimum area, delay and power

EDTC '96 Proceedings of the 1996 European conference on Design and Test

An efficient algorithm for finding the minimal-area FPGA technology mapping

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Logic synthesis based on decomposition for CPLDs

Microprocessors & Microsystems

Decomposition-based logic synthesis for PAL-based CPLDs

International Journal of Applied Mathematics and Computer Science