EURO-DAC '92 Proceedings of the conference on European design automation
Optimum functional decomposition using encoding
DAC '94 Proceedings of the 31st annual Design Automation Conference
Technology mapping for large complex PLDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Graph coloring algorithms for fast evaluation of Curtis decompositions
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A new techology mapping for CPLD under the time constraint
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Functional Decomposition with Application to FPGA Synthesis
Functional Decomposition with Application to FPGA Synthesis
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Sequential Logic Synthesis
FPGA Synthesis Using Function Decomposition
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
An Input-Output Encoding Approach for Serial Decomposition
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
An Improved Input-Output Encoding Approach for Functional Decomposition
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
EURO-DAC '90 Proceedings of the conference on European design automation
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact algorithms for output encoding, state assignment, and four-level Boolean minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PLADE: a two-stage PLA decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Satisfaction of input and output encoding constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The paper presents a decomposition method dedicated for PAL based CPLDs. Non-standard usage of decomposition, which leads to the minimization of area in an implemented circuit and the reduction of used logic blocks in a programmable structure, is the aim of the proposed method. Each decomposition step (bound set selection, graph colouring, column pattern coding, etc.) is oriented for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The proposed decomposition method is an extension of the classical approach, commonly thought to be adequately efficient. Experiments carried out on typical benchmarks show significant area reduction.