Multi-level synthesis on PALs

Authors:
Gabrielle Saucier;Pascal Sicard;Laurent Bouchet
Affiliations:
Institut National Polytechnique de Grenoble, 46 avenue Felix Viallet, 38031 Grenoble Cedex_France;Institut National Polytechnique de Grenoble, 46 avenue Felix Viallet, 38031 Grenoble Cedex_France;Laboratoire d'Annecy-le-vieux de Physique des Particules, Chemin de Bellevue BP 110, 74941 Annecy-Le-Vieux Cedex_France
Venue:
EURO-DAC '90 Proceedings of the conference on European design automation
Year:
1990

Citing 5
Cited 3

PALMINI—fast Boolean minimizer for personal computers

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Automatic synthesis of Boolean equations using programmable array logic

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The McBOOLE logic minimizer

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis
Factoring logic functions

IBM Journal of Research and Development - Mathematics and computing

FPGA design principles (a tutorial)

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
PLATO: a CAD tool for logic synthesis based on decomposition

EURO-DAC '91 Proceedings of the conference on European design automation
Logic synthesis based on decomposition for CPLDs

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a decomposition method for logic mapping on PALs. It addresses a large variety of PALs. For functions having too many variables, a novel approach based on algebraic divisions is proposed. It is followed by an interesting reinjection phase tending to suppress unusefull decompositions. Both critical path and PAL numbers are optimised.