PLATO: a CAD tool for logic synthesis based on decomposition

Authors:
Tedeusz Luba;Jerzy Kalinowski;Krzysztof Jasiński
Affiliations:
Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warszawa, Poland;Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warszawa, Poland;Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warszawa, Poland
Venue:
EURO-DAC '91 Proceedings of the conference on European design automation
Year:
1991

Citing 3
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Abstract

In this paper a CAD system for logic synthesis (PLATO system) that exploits logic decomposition to optimize the actual circuit is presented. Unlike the traditional approach, where the partitioning or decomposition follows logic minimization, decomposition process is carried out in the PLATO system as the very first step in the logic synthesis. Experimental results indicate that a significant reduction of the silicon area can be obtained using this new design strategy.