Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Derivation of Minimal Sums for Completely Specified Functions
IEEE Transactions on Computers
Generating Essential Primes for a Boolean Function with Multiple-Valued Inputs
IEEE Transactions on Computers
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
An overview of logic synthesis systems
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On the verification of sequential machines at differing levels of abstraction
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logic verification algorithms and their parallel implementation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
BIST-PLA: a built-in self-test design of large programmable logic arrays
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Function search from behavioral description of a digital system
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A parallel PLA minimization program
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
PALMINI—fast Boolean minimizer for personal computers
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Functional Test Generation Based on Unate Function Theory
IEEE Transactions on Computers
On the Design of Pseudoexhaustive Testable PLAs
IEEE Transactions on Computers - Fault-Tolerant Computing
Anatomy of a hardware compiler
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
SOCRATES: A system for automatically synthesizing and optimizing combinational logic
25 years of DAC Papers on Twenty-five years of electronic design automation
On the Size of PLAs Required to Realize Binary and Multiple-Valued Functions
IEEE Transactions on Computers
A New Approach to Realizing Partially Symmetric Functions
IEEE Transactions on Computers
Multi-level logic synthesis using communication complexity
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
New methods in the analysis of logic minimization data and algorithms
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Multi-level logic simplification using don't cares and filters
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
NOVA: state assignment of finite state machines for optimal two-level logic implementations
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Horizontal partitioning of PLA-based finite state machines
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A functional-level test generation methodology using two-level representations
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
On the Design of High-Yield Reconfigurable PLA's
IEEE Transactions on Computers
Symbolic prime generation for multiple-valued functions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Implicit and incremental computation of primes and essential primes of Boolean functions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On the over-specification problem in sequential ATPG algorithms
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automatic Test Pattern Generation with Branch Testing
IEEE Transactions on Computers
Minimization Algorithms for Multiple-Valued Programmable Logic Arrays
IEEE Transactions on Computers
Absolute Minimization of Completely Specified Switching Functions
IEEE Transactions on Computers
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation
IEEE Transactions on Computers
RIDDLE: A Foundation for Test Generation on a High-Level Design Description
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Verification of interacting sequential circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Test function specification in synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Boolean resubstitution with permissible functions and binary decision diagrams
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Reduced offsets for two-level multi-valued logic minimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Design of repairable and fully diagnosable folded PLAs for yield enhancement
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic optimization algorithm by linear programming approach
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Abstract data types and high-level synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
BIST PLAs, pass or fail—a case study
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A framework for satisfying input and output encoding constraints
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
FSM decomposition revisited: Algebraic structure theory applied to MCNC benchmark FSMs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A CAD system for the design of field programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Utilizing logic information in multi-level timing simulation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Algorithms for synthesis of hazard-free asynchronous circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Bridging high-level synthesis to RTL technology libraries
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Initializability Consideration in Sequential Machine Synthesis
IEEE Transactions on Computers
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
ISSAC '92 Papers from the international symposium on Symbolic and algebraic computation
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An improved synthesis algorithm for multiplexor-based PGA's
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Efficient sum-to-one subsets algorithm for logic optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Optimization of primitive gate networks using multiple output two-level minimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Recurrence equations and the optimization of synchronous logic circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Control optimization in high-level synthesis using behavioral don't cares
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Flexible controlpath microarchitecture synthesis based on artificial intelligence
EURO-DAC '92 Proceedings of the conference on European design automation
Maximal reduction of lookup-table based FPGAs
EURO-DAC '92 Proceedings of the conference on European design automation
Experiments on the synthesis and testability of non-scan finite state machines
EURO-DAC '92 Proceedings of the conference on European design automation
State assignment for hardwired VLSI control units
ACM Computing Surveys (CSUR)
INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning
DAC '93 Proceedings of the 30th international Design Automation Conference
The sea-of-wires array synthesis system
DAC '93 Proceedings of the 30th international Design Automation Conference
Espresso-signature: a new exact minimizer for logic functions
DAC '93 Proceedings of the 30th international Design Automation Conference
A new viewpoint on two-level logic minimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Parallelizing complex scans and reductions
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An efficient procedure for the synthesis of fast self-testable controller structures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Random pattern testable logic synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level synthesis for safe replaceability
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On error correction in macro-based circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Circuit partitioning for huge logic emulation systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimum functional decomposition using encoding
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Fast OFDD based minimization of fixed polarity Reed-Muller expressions
EURO-DAC '94 Proceedings of the conference on European design automation
Testing redundant asynchronous circuits by variable phase splitting
EURO-DAC '94 Proceedings of the conference on European design automation
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
High-level synthesis in an industrial environment
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A fast state assignment procedure for large FSMs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New ideas for solving covering problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A partitioning-based logic optimization method for large scale circuits with Boolean matrix
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Activity-sensitive architectural power analysis for the control path
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient use of large don't cares in high-level and logic synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Boolean techniques for low power driven re-synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Two-level logic minimization for low power
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Functional test generation for delay faults in combinational circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Negation Trees: A Unified Approach to Boolean Function Complementation
IEEE Transactions on Computers
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generalized Partially-Mixed-Polarity Reed-Muller Expansion and Its Fast Computation
IEEE Transactions on Computers
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
HDL optimization using timed decision tables
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Espresso-HF: a heuristic hazard-free minimizer for two-level logic
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Multilevel logic synthesis for arithmetic functions
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A fast state reduction algorithm for incompletely specified finite state machine
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic mapping of neurons in feedforward networks
Pattern Recognition Letters
Multi-level logic optimization for low power using local logic transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Fast OFDD-Based Minimization of Fixed Polarity Reed-Muller Expressions
IEEE Transactions on Computers
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simulation based architectural power estimation for PLA-based controllers
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
High-level power estimation and the area complexity of Boolean functions
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Cube-packing and two-level minimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Boolean factorization using multiple-valued minimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Maximum projections of don't care conditions in a Boolean network
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Signed Binary Addition Circuitry with Inherent Even Parity Outputs
IEEE Transactions on Computers
A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimizing designs containing black boxes
DAC '97 Proceedings of the 34th annual Design Automation Conference
Potential-driven statistical ordering of transformations
DAC '97 Proceedings of the 34th annual Design Automation Conference
A fast and robust exact algorithm for face embedding
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An output encoding problem and a solution technique
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Trace driven logic synthesis—application to power minimization
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The future of logic synthesis and physical design in deep-submicron process geometries
Proceedings of the 1997 international symposium on Physical design
Cluster-cover: a theoretical framework for a class of VLSI-CAD optimization problems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Solving Boolean Equations Using ROSOP Forms
IEEE Transactions on Computers
A methodology for guided behavioral-level optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
M32: a constructive multilevel logic synthesis system
DAC '98 Proceedings of the 35th annual Design Automation Conference
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
A defect-tolerant and fully testable PLA
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
PLAYGROUND: minimization of PLAs with mixed ground true outputs
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Deriving Petri Nets from Finite Transition Systems
IEEE Transactions on Computers
Finding all simple disjunctive decompositions using irredundant sum-of-products forms
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Don't Care discovery for FPGA configuration compression
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
On Variable Ordering and Decomposition Type Choice in OKFDDs
IEEE Transactions on Computers
Two-level logic minimization for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power reduction and power-delay trade-offs using logic transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation
Journal of Electronic Testing: Theory and Applications
Exhaustive simulation need not require an exponential number of tests
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Exact Minimization of Binary Decision Diagrams Using Implicit Techniques
IEEE Transactions on Computers
FreezeFrame: compact test generation using a frozen clock strategy
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Behavioral synthesis of combinational logic using spectral-based heuristics
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Deterministic BIST with Multiple Scan Chains
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Doing two-level logic minimization 100 times faster
Proceedings of the sixth annual ACM-SIAM symposium on Discrete algorithms
PLATYPUS: a PLA test pattern generation tool
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Synthesis techniques for digital systems design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Symbolic manipulation of Boolean functions using a graphical representation
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
PHIPLA—a new algorithm for logic minimization
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Generating essential primes for a Boolean function with multiple-valued inputs
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Mixed-level fault coverage estimation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
GENIE: a generalized array optimizer for VLSI synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Comparison of CMOS PLA and polycell representations of control logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An implementation of a state assignment heuristic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Pseudo-Kronecker Expressions for Symmetric Functions
IEEE Transactions on Computers
Macro-driven circuit design methodology for high-performance datapaths
Proceedings of the 37th Annual Design Automation Conference
Testability of 2-Level AND/EXOR Circuits
Journal of Electronic Testing: Theory and Applications
A BDD-based satisfiability infrastructure using the unate recursive paradigm
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An efficient heuristic approach to solve the unate covering problem
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Deterministic BIST with Partial Scan
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Minimized Power Consumption for Scan-Based BIST
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
An integrated approach to accelerate data and predicate computations in hyperblocks
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
An efficient learning procedure for multiple implication checks
Proceedings of the conference on Design, automation and test in Europe
On applying the set covering model to reseeding
Proceedings of the conference on Design, automation and test in Europe
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits
IEEE Transactions on Computers
On the minimization of SOPs for bi-decomposition functions
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Synthesis of single-output space compactors with application to scan-based IP cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
HW/SW partitioning of an embedded instruction memory decompressor
Proceedings of the ninth international symposium on Hardware/software codesign
TAO: regular expression-based register-transfer level testability analysis and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Worst and Best Irredundant Sum-of-Products Expressions
IEEE Transactions on Computers
Logic Synthesis and Verification
Multi-level logic optimization
Logic Synthesis and Verification
Logic Synthesis and Verification
SAT and ATPG: algorithms for Boolean decision problems
Logic Synthesis and Verification
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Compressing inverted files in scalable information systems by binary decision diagram encoding
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
A SAT Solver Using Reconfigurable Hardware and Virtual Logic
Journal of Automated Reasoning
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
BOOM: a heuristic boolean minimizer
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Computers and Operations Research
BDD-based logic synthesis for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application of Deterministic Logic BIST on Industrial Circuits
Journal of Electronic Testing: Theory and Applications
Designing Circuits with Partial Scan
IEEE Design & Test
Behavioral Model Synthesis with Cones
IEEE Design & Test
Analysis of Testable PLA Designs
IEEE Design & Test
Routing Table Compaction in Ternary CAM
IEEE Micro
Minimization of AND-EXOR Expressions Using Rewrite Rules
IEEE Transactions on Computers
Design of Pseudoexhaustive Testable PLA with Low Overhead
IEEE Transactions on Computers
Testing of Fault-Tolerant Hardware Through Partial Control of Inputs
IEEE Transactions on Computers
Two-Level Minimization of Multivalued Functions with Large Offsets
IEEE Transactions on Computers
A State Assignment Approach to Asynchronous CMOS Circuit Design
IEEE Transactions on Computers
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing
IEEE Transactions on Computers
Zero-Aliasing for Modeled Faults
IEEE Transactions on Computers
R-MINI: An Iterative Approach for Generating Minimal Rules from Examples
IEEE Transactions on Knowledge and Data Engineering
Symbolic Interpretation of Artificial Neural Networks
IEEE Transactions on Knowledge and Data Engineering
Binary Rule Generation via Hamming Clustering
IEEE Transactions on Knowledge and Data Engineering
A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Evolutionary algorithms for the satisfiability problem
Evolutionary Computation
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Morphological Operations on 3D and 4D Images: From Shape Primitive Detection to Skeletonization
DGCI '00 Proceedings of the 9th International Conference on Discrete Geometry for Computer Imagery
Sequential optimization in the absence of global reset
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Whirlpool PLAs: a regular logic structure and their synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Simplification of non-deterministic multi-valued networks
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Large-scale SOP minimization using decomposition and functional properties
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
Fanout fault analysis for digital logic circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Functional test generation for path delay faults
ATS '95 Proceedings of the 4th Asian Test Symposium
Automatic synthesis of gate-level timed circuits with choice
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A BIST approach to delay fault testing with reduced test length
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Solving Graph Optimization Problems with ZBDDs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Testability of 2-level AND/EXOR circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A new switching-level approach to multiple-output functions synthesis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Logic minimization based approach for compressing image data
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Cubical CAMP for minimization of Boolean functions
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Retiming with logic duplication transformation: theory and an application to partial scan
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Simultaneous Circuit Transformation and Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Low-Energy BIST Design for Scan-based Logic Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Methods to reduce test application time for accumulator-based self-test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Using BIST Control for Pattern Generation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Efficient Design Error Correction of Digital Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Decomposition of Multiple-Valued Functions
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A codesigned on-chip logic minimizer
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Technology mapping using boolean matching and don't care sets
EURO-DAC '90 Proceedings of the conference on European design automation
A new synthesis technique for multilevel combinational circuits
EURO-DAC '90 Proceedings of the conference on European design automation
EURO-DAC '90 Proceedings of the conference on European design automation
State assignment of controllers for optimal area implementation
EURO-DAC '90 Proceedings of the conference on European design automation
An architecture for synthesis of testable finite state machines
EURO-DAC '90 Proceedings of the conference on European design automation
CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler
EURO-DAC '90 Proceedings of the conference on European design automation
The effectiveness of different test sets for PLAs
EURO-DAC '90 Proceedings of the conference on European design automation
Design for verification testability
EURO-DAC '90 Proceedings of the conference on European design automation
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Synthesis of multi-level logic with one symbolic input
EURO-DAC '91 Proceedings of the conference on European design automation
PLATO: a CAD tool for logic synthesis based on decomposition
EURO-DAC '91 Proceedings of the conference on European design automation
Detection of PLA multiple crosspoint faults
EURO-DAC '91 Proceedings of the conference on European design automation
Synthesis of fully testable sequential machines
EURO-DAC '91 Proceedings of the conference on European design automation
MACHETE: synthesis of sequential machines for easy testability
EURO-DAC '91 Proceedings of the conference on European design automation
Functional abstraction of logic gates for switch-level simulation
EURO-DAC '91 Proceedings of the conference on European design automation
Optimization of micro-controllers by partitioning
EURO-DAC '91 Proceedings of the conference on European design automation
A self-checking PLA automatic generator tool based on unordered codes encoding
EURO-DAC '91 Proceedings of the conference on European design automation
Module synthesis for finite state machines
EURO-DAC '91 Proceedings of the conference on European design automation
Class-Based Decompressor Design for Compressed Instruction Memory in Embedded Processors
IEEE Transactions on Computers
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
IEEE Transactions on Computers
Design of combinational logic circuits through an evolutionary multiobjective optimization approach
Artificial Intelligence for Engineering Design, Analysis and Manufacturing
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A magnetoelectronic macrocell employing reconfigurable threshold logic
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Morphological operations in recursive neighborhoods
Pattern Recognition Letters - Special issue: Discrete geometry for computer imagery (DGCI'2002)
A timing-driven module-based chip design flow
Proceedings of the 41st annual Design Automation Conference
A robust algorithm for approximate compatible observability don't care (CODC) computation
Proceedings of the 41st annual Design Automation Conference
A Theory of Non-Deterministic Networks
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IBM Journal of Research and Development - Mathematics and computing
A fast method to derive minimum SOPs for decomposable functions
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Reducing Multi-Valued Algebraic Operations to Binary
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EaseCAM: An Energy and Storage Efficient TCAM-Based Router Architecture for IP Lookup
IEEE Transactions on Computers
A new approach to the use of satisfiability in false path detection
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Encyclopedia of Computer Science
Temporal Decomposition for Logic Optimization
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Variable Length Representation in Evolutionary Electronics
Evolutionary Computation
M-trie: an efficient approach to on-chip logic minimization
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Integrating CNF and BDD based SAT solvers
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
ACM-SE 38 Proceedings of the 38th annual on Southeast regional conference
A design flow to optimize circuit delay by using standard cells and PLAs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Efficient minimization of fully testable 2-SPP networks
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A hybridized genetic parallel programming based logic circuit synthesizer
Proceedings of the 8th annual conference on Genetic and evolutionary computation
A PLA based asynchronous micropipelining approach for subthreshold circuit design
Proceedings of the 43rd annual Design Automation Conference
Structured and tuned array generation (STAG) for high-performance random logic
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Synthesis of irregular combinational functions with large don't care sets
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A high-level requirements engineering methodology for electronic system-level design
Computers and Electrical Engineering
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Engineering trust with semantic guardians
Proceedings of the conference on Design, automation and test in Europe
Fuzzy modelling through logic optimization
International Journal of Approximate Reasoning
BerkMin: A fast and robust Sat-solver
Discrete Applied Mathematics
DDBDD: delay-driven BDD synthesis for FPGAs
Proceedings of the 44th annual Design Automation Conference
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
Journal of VLSI Signal Processing Systems
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The decomposition tree for analyses of boolean functions
Mathematical Structures in Computer Science
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
Pipelined network of PLA based circuit design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Dependable design technique for system-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
An efficient approach to on-chip logic minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal complexity reduction of polyhedral piecewise affine systems
Automatica (Journal of IFAC)
Analysis of a genetic programming algorithm for association studies
Proceedings of the 10th annual conference on Genetic and evolutionary computation
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
A purely map procedure for two-level multiple-output logic minimization
International Journal of Computer Mathematics
Column-matching based mixed-mode test pattern generator design technique for BIST
Microprocessors & Microsystems
On the construction of small fully testable circuits with low depth
Microprocessors & Microsystems
Pattern minimization problems over recursive data types
Proceedings of the 13th ACM SIGPLAN international conference on Functional programming
Formal techniques used in encrypting systems
EC'08 Proceedings of the 9th WSEAS International Conference on Evolutionary Computing
Matching Integer Intervals by Minimal Sets of Binary Words with don't cares
CPM '08 Proceedings of the 19th annual symposium on Combinatorial Pattern Matching
Closed patterns meet n-ary relations
ACM Transactions on Knowledge Discovery from Data (TKDD)
A novel approach for fast covering the Boolean sets
ISTASC'08 Proceedings of the 8th conference on Systems theory and scientific computation
On the numbers of variables to represent sparse logic functions
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Robust window-based multi-node technology-independent logic minimization
Proceedings of the 19th ACM Great Lakes symposium on VLSI
High speed gate level synchronous full adder designs
WSEAS Transactions on Circuits and Systems
Integration, the VLSI Journal
Domain dependence in parallel constraint satisfaction
IJCAI'89 Proceedings of the 11th international joint conference on Artificial intelligence - Volume 1
A delay improved gate level full adder design
ECC'09 Proceedings of the 3rd international conference on European computing conference
A logically complete reasoning maintenance system based on a logical constraint solver
IJCAI'91 Proceedings of the 12th international joint conference on Artificial intelligence - Volume 1
Journal of Artificial Intelligence Research
Design innovation for real world applications, using evolutionary algorithms
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Gate-level optimization of polymorphic circuits using Cartesian genetic programming
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
iCOACH: A circuit optimization aid for CMOS high-performance circuits
Integration, the VLSI Journal
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FSM Encoding for BDD Representations
International Journal of Applied Mathematics and Computer Science
Fusing mobile, sensor, and social data to fully enable context-aware computing
Proceedings of the Eleventh Workshop on Mobile Computing Systems & Applications
RECOMB'07 Proceedings of the 11th annual international conference on Research in computational molecular biology
A note on designing logical circuits using SAT
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improvements on the detection of false paths by using unateness and satisfiability
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
AAAI'90 Proceedings of the eighth National conference on Artificial intelligence - Volume 1
A memory- and time-efficient on-chip TCAM minimizer for IP lookup
Proceedings of the Conference on Design, Automation and Test in Europe
Approximate logic synthesis for error tolerant applications
Proceedings of the Conference on Design, Automation and Test in Europe
Diagnosing multiple intermittent failures using maximum likelihood estimation
Artificial Intelligence
On decomposing Boolean functions via extended cofactoring
Proceedings of the Conference on Design, Automation and Test in Europe
Control strategies for chip-based DFT/BIST hardware
ITC'94 Proceedings of the 1994 international conference on Test
Optimal logic synthesis and testability: two faces of the same coin
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Dynamic techniques for yield enhancement of field programmable logic arrays
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An algorithmic branch and bound method for PLA test pattern generation
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Quantum Information Processing
A set theory based method to derive network reliability expressions of complex system topologies
ACC'10 Proceedings of the 2010 international conference on Applied computing conference
A Boolean function approach to feature selection in consistent decision information systems
Expert Systems with Applications: An International Journal
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
ECS'10/ECCTD'10/ECCOM'10/ECCS'10 Proceedings of the European conference of systems, and European conference of circuits technology and devices, and European conference of communications, and European conference on Computer science
A relational approach to functional decomposition of logic circuits
ACM Transactions on Database Systems (TODS)
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
WSEAS Transactions on Circuits and Systems
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
Block-oriented programmable design with switching network interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance-driven synthesis in controller-datapath systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On methods to match a test pattern generator to a circuit-under-test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Advances in Engineering Software
Computers in Biology and Medicine
Design of fuzzy rule-based classifiers with semantic cointension
Information Sciences: an International Journal
Genetic Programming and Evolvable Machines
Generating understandable and accurate fuzzy rule-based systems in a java environment
WILF'11 Proceedings of the 9th international conference on Fuzzy logic and applications
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Decomposition-based logic synthesis for PAL-based CPLDs
International Journal of Applied Mathematics and Computer Science
A method for minimizing Moore finite-state machines by merging two states
Journal of Computer and Systems Sciences International
Synthesis of parallel binary machines
Proceedings of the International Conference on Computer-Aided Design
An evolutionary local search algorithm for the satisfiability problem
TAINN'05 Proceedings of the 14th Turkish conference on Artificial Intelligence and Neural Networks
Improvements of the construction of exact minimal covers of boolean functions
EUROCAST'11 Proceedings of the 13th international conference on Computer Aided Systems Theory - Volume Part II
Minimization of mealy finite-state machines by internal states gluing
Journal of Computer and Systems Sciences International
Efficient synthesis of feature models
Proceedings of the 16th International Software Product Line Conference - Volume 1
An excursion in reaction systems: From computer science to biology
Theoretical Computer Science
Virtual scan chains reordering using a RAM-based module for high test compression
Microelectronics Journal
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Journal of Electronic Testing: Theory and Applications
Managing hybrid packet filter's specifications
International Journal of Security and Networks
Rule extraction from ensemble methods using aggregated decision trees
ICONIP'12 Proceedings of the 19th international conference on Neural Information Processing - Volume Part II
Reversible logic synthesis of k-input, m-output lookup tables
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic behavior of cell signaling networks: model design and analysis automation
Proceedings of the 50th Annual Design Automation Conference
NEQR: a novel enhanced quantum representation of digital images
Quantum Information Processing
Efficient gray-code-based range encoding schemes for packet classification in TCAM
IEEE/ACM Transactions on Networking (TON)
Machine-learning-based circuit synthesis
IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence
Encoding multi-valued functions for symmetry
Proceedings of the International Conference on Computer-Aided Design
Dual-rail asynchronous logic multi-level implementation
Integration, the VLSI Journal
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