DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Test function specification in synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A unified approach for the synthesis of self-testable finite state machines
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Design for Testability Using State Distances
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Test scheduling and controller synthesis in the CADDY-system
EURO-DAC '91 Proceedings of the conference on European design automation
MACHETE: synthesis of sequential machines for easy testability
EURO-DAC '91 Proceedings of the conference on European design automation
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We present a hardware architecture for synthesizing finite state machines (FSM). This architecture is defined at the level of the state transition graph. It contains a test machine with the same number of state variables as the object machine to be synthesized. The state graph of the test machine is so defined that each state is uniquely set and observed by input sequence no longer than [logkn], where n is the number of states and the integer k is a design parameter. The state transition graph of the test machine is superposed on the given state graph of the object function. The logic implementation steps, namely, state assignment, minimization and technology mapping are carried out for the combined graph. By design, the embedded test machine is fully testable. Also, since the test machine can control all memory elements, the circuit is effectively tested by a combinational circuit test generator. Scan register is shown to be a special case of the presented methodology.