A unified approach for the synthesis of self-testable finite state machines

Authors:
Bernhard Eschermann;Hans-Joachim Wunderlich
Affiliations:
Institut für Rechnerentwurf und Fehlertoleranz, Universität Karlsruhe, Germany;Institut für Rechnerentwurf und Fehlertoleranz, Universität Karlsruhe, Germany
Venue:
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Year:
1991

CrossCheck: a cell based VLSI testability solution

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A kernel-finding state assignment algorithm for multi-level logic

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An architecture for synthesis of testable finite state machines

EURO-DAC '90 Proceedings of the conference on European design automation

Hi-index	0.00