Finite state machine synthesis with embedded test function
Journal of Electronic Testing: Theory and Applications
A unified approach for the synthesis of self-testable finite state machines
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Finite state machine synthesis with fault tolerant test function
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A structure and technique for pseudorandom-based testing of sequential circuits
Journal of Electronic Testing: Theory and Applications
A fast state assignment procedure for large FSMs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
SINMEF - A Decomposition Based Synthesis Tool for Large FSMs
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ICCD '98 Proceedings of the International Conference on Computer Design
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis
ATS '01 Proceedings of the 10th Asian Test Symposium
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware-optimal test register insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A comprehensive approach to the partial scan problem using implicit state enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
This paper reports a novel approach to design efficient BIST structures for sequential machines (FSMs) with reduced gate area. In a PRPG based BIST structure, an FSM shows limited testability due to three kinds of states, viz., the unreachable states, the hard-to-exit states, and the hard-to-reach states. A metric, referred to as degree-of-freedom (DOF) in FSM states has been introduced that quantifies the BIST quality of an FSM. Analysis of DOF enables efficient state encoding to ensure high BIST quality as well as low gate area of the resulting FSM. A genetic algorithm (GA) based graph embedding approach is adopted to solve the state encoding problem. Experimental results on benchmark circuits show that the proposed scheme improves the BIST quality significantly simultaneously reducing the gate area of the resultant machine.