Freeze!: a new approach for testing sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A structure and technique for pseudorandom-based testing of sequential circuits
Journal of Electronic Testing: Theory and Applications
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Built-in generation of weighted test sequences for synchronous sequential circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
ETW '00 Proceedings of the IEEE European Test Workshop
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Journal of Electronic Testing: Theory and Applications
Efficient BIST design for sequential machines using FiF-FoF values in machine states
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed test application. We introduce a uniform, parametrized structure for test pattern generation. By matching the parameters of the test pattern generator to the circuit-under-test, high fault coverage is achieved. In many cases, the fault coverage is equal to the fault coverage that can be achieved by deterministic test sequences. We also investigate a method to minimize the size of the test pattern generator, and study its effectiveness alone and in conjunction with the insertion of test-points.