Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
A structure and technique for pseudorandom-based testing of sequential circuits
Journal of Electronic Testing: Theory and Applications
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences
IEEE Transactions on Computers
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An algorithm to reduce test application time in full scan designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
On Combining Design for Testability Techniques
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Fast Sequential ATPG Based on Implicit State Enumeration
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Warning: 100% Fault Coverage May Be Misleading!!
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On Selecting Flip-Flops for Partial Reset
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Full-Symbolic ATPG for Large Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
On the Detection of Reset Faults in Synchronous Sequential Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
On the effects of test compaction on defect coverage
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Vector restoration based static compaction of test sequences for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Full scan design renders every combinationally irredundant fault in a synchronous sequential circuit testable. In this paper, we derive a similar result applicable to design-for-testability techniques that only control the initial state of the circuit in order to improve its testability. Examples of such techniques are parallel load, reset, and scan when it is used only to set the state of the circuit. We show that if the initial state can be set arbitrarily, a test sequence can be generated for every irredundant fault, i.e., for every fault that is not sequentially or combinationally redundant. Thus, the ability to control the state of the circuit is sufficient for detecting every irredundant fault and observability of the circuit state is not necessary for this purpose. When considering scan, this result implies that scan-out can be used to control the test length and test generation time, but it is not necessary for detecting irredundant faults. We also show that, of all the states of the circuit, it is sufficient to consider as possible initial states (or controllable states) only the states extracted from a complete combinational test set. We demonstrate the use of these observations by presenting experimental results of two applications. In the first application, initial states are selected out of a combinational test set to facilitate deterministic test generation for irredundant faults. In the second application, the ability to set the initial state is used to increase the effectiveness of built-in self-test.