The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Fast Sequential ATPG Based on Implicit State Enumeration
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Full-Symbolic ATPG for Large Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
On the use of reset to increase the testability of interconnected finite-state machines
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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We consider the problem of testing reset faults in synchronous sequential circuits with reset hardware. The reset hardware is assumed to consist of a reset input connected to all the flip-flops through a reset line. We propose a fault model that accommodates any routing of the reset line to the flip-flops. This is important since test generation is typically carried out without knowledge of the way in which the reset line is routed. We describe fault simulation procedures for the proposed reset fault model. The procedures use a given test sequence and generate appropriate reset sequences, if needed. It is shown that contrary to the common assumption that reset faults are easily detected by test sequences for other faults in the circuit some reset faults require special reset sequences and special test sequences. Thus, a complete test sequence must explicitly accommodate reset faults.