Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
Testable synthesis of high complex control devices
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
The maximum set of permissible behaviors for FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Input don't care sequences in FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On the Detection of Reset Faults in Synchronous Sequential Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Test function embedding algorithms with application to interconnected finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A partition and resynthesis approach to testable design of large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We propose a DFT solution for synchronous sequential circuits described as interconnections of finite-state machines, that takes into account specific requirements for justification of test sequences and propagation of fault effects occurring during test generation. We present this solution in the context of the output sequence justification problem. The proposed DFT solution is based on the use of reset. Three types of reset mechanisms are considered, having increasing overhead and increasing flexibility. The third type allows every output sequence over the output alphabet of a machine to be justified.