Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Testable synthesis of high complex control devices
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
The maximum set of permissible behaviors for FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Input don't care sequences in FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
IEEE Transactions on Computers
On the use of reset to increase the testability of interconnected finite-state machines
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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Test generation for synchronous sequential circuits can be facilitated by decomposing the circuit into a cycle free interconnection of submachines, such that all feedback loops are included within the submachines. In this work, we describe a test generation procedure that takes advantage of cycle free circuit decomposition. The paper focuses on one of the subproblems of the test generation problem, the output sequence justification problem. We propose a solution to this problem and show how it can be incorporated into a test generation procedure.