Logic testing and design for testability
Logic testing and design for testability
Finite state machine synthesis with embedded test function
Journal of Electronic Testing: Theory and Applications
Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A Synthesis Approach to Design for Testability
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Sequential logic minimization based on functional testability
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Functional design for testability of control-dominated architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On the use of reset to increase the testability of interconnected finite-state machines
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A complete testing strategy based on interacting and hierarchical FSMs
Integration, the VLSI Journal
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