Fast Sequential ATPG Based on Implicit State Enumeration
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Testable synthesis of high complex control devices
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Functional design for testability of control-dominated architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a methodology for sequential logic minimization based on a functional testing approach. A new class of sequentially redundant faults, called functionally redundant, is defined. Such faults are determined by analyzing the functional description of a circuit; their identification and removal is the main topic of the paper. We show that by comparing the gate-level implementation of a circuit with its functional description, it is possible to produce fully testable circuits by spending a fraction of the time usually necessary for applying standard redundancies removal algorithms working at the gate level.