A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Finite state machine synthesis with embedded test function
Journal of Electronic Testing: Theory and Applications
Testable synthesis of high complex control devices
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
BDD-based testability estimation of VHDL designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Sequential logic minimization based on functional testability
EDTC '95 Proceedings of the 1995 European conference on Design and Test
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Test function embedding algorithms with application to interconnected finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A partition and resynthesis approach to testable design of large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
Testing Core-Based Systems: A Symbolic Methodology
IEEE Design & Test
Automatic Functional Vector Generation Using the Interacting FSM Model
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
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Control-dominated architectures are usually described in a hardware description language (HDL) by means of interacting FSMs. A VHDL or Verilog specification can be translated into an interacting FSM (IFSM) representation as described here. The IFSM model allows us to approach the testable synthesis problem at the level of each FSM. The functionality is modified by the addition of transparency to data flow. The complete testability of the IFSM implementation is thus achieved by connecting fully testable implementations of each modified FSM. In this way, test sequences separately generated for each FSM are directly applied to the IFSM to achieve complete fault coverage. The addition of test functionality to each FSM description, and its simultaneous synthesis with the FSM functionality, produces a lower area overhead than that necessary for the application of a partial-scan technique. Moreover, the test generation problem is highly simplified since it is reduced to the test generation for each separate FSM.