A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Split circuit model for test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
Accelerated test pattern generation by cone-oriented circuit partitioning
EURO-DAC '90 Proceedings of the conference on European design automation
APT: an area-performance-testability driven placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Freeze!: a new approach for testing sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Parallel test generation for sequential circuits on general-purpose multiprocessors
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Hierarchical test generation under intensive global functional constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Exact evaluation of diagnostic test resolution
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Cellular scan test generation for sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning
DAC '93 Proceedings of the 30th international Design Automation Conference
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
A state traversal algorithm using a state covariance matrix
DAC '93 Proceedings of the 30th international Design Automation Conference
Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
DAC '93 Proceedings of the 30th international Design Automation Conference
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Selecting partial scan flip-flops for circuit partitioning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Optimizing resource utilization and testability using hot potato techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
ProperHITEC: a portable, parallel, object-oriented approach to sequential test generation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Symbolic exploration of large circuits with enhanced forward/backward traversals
EURO-DAC '94 Proceedings of the conference on European design automation
Rapid diagnostic fault simulation of stuck-at faults in sequential circuits using compact lists
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On test set preservation of retimed circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Partial scan selection for user-specified fault coverage
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Identification of unsettable flip-flops for partial scan and faster ATPG
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
BDD-based testability estimation of VHDL designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Functional design for testability of control-dominated architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploiting hardware sharing in high-level synthesis for partial scan optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Fault dictionary compression and equivalence class computation for sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Design for Testability Using State Distances
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Algorithms to compute bridging fault coverage of IDDQ test sets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hierarchical test generation and design for testability of ASPPs and ASIPs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fault simulation under the multiple observation time approach using backward implications
DAC '97 Proceedings of the 34th annual Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
A Novel Approach to Random Pattern Testing of Sequential Circuits
IEEE Transactions on Computers
DAC '98 Proceedings of the 35th annual Design Automation Conference
Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Static compaction using overlapped restoration and segment pruning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A fast, accurate, and non-statistical method for fault coverage estimation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast Static Compaction Algorithms for Sequential Circuit Test Vectors
IEEE Transactions on Computers
Efficient Techniques for Dynamic Test Sequence Compaction
IEEE Transactions on Computers
RTL Test Justification and Propagation Analysis for Modular Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Synthesis of Native Mode Self-Test Programs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A comparative study of design for testability methods using high-level and gate-level descriptions
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Initialization of Sequential Circuits and its Application to ATPG
Journal of Electronic Testing: Theory and Applications
Sequential circuit test generation using decision diagram models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Illegal state space identification for sequential circuit test generation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
FreezeFrame: compact test generation using a frozen clock strategy
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exploiting Behavioral Information in Gate-Level ATPG
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multiple error diagnosis based on xlists
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits
SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
A Hierarchical Test Generation Approach for Large Controllers
IEEE Transactions on Computers
Hybrid Fault Simulation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
On Non-Statistical Techniques for Fast Fault Coverage Estimation
Journal of Electronic Testing: Theory and Applications
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams
Proceedings of the 37th Annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Techniques for improving the efficiency of sequential circuit test generation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A framework for testing core-based systems-on-a-chip
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An approach for improving the levels of compaction achieved by vector omission
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits
IEEE Transactions on Computers
Dynamic state traversal for sequential circuit test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Compaction of IDDQ Test Sequence Using Reassignment Method
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Test Set Compaction Using Relaxed Subsequence Removal
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
A Practical Vector Restoration Technique for Large Sequential Circuits
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Efficient spectral techniques for sequential ATPG
Proceedings of the conference on Design, automation and test in Europe
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Fast sequential circuit test generation using high-level and gate-level techniques
Proceedings of the conference on Design, automation and test in Europe
State relaxation based subsequence removal for fast static compaction in sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Exploiting symbolic techniques for partial scan flip flop selection
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 14th international symposium on Systems synthesis
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An exact solution to the minimum size test pattern problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TAO: regular expression-based register-transfer level testability analysis and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
Effective safety property checking using simulation-based sequential ATPG
Proceedings of the 39th annual Design Automation Conference
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Proceedings of the 1994 ACM/IEEE conference on Supercomputing
Deterministic test pattern generation techniques for sequential circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Min-area retiming on flexible circuit structures
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
On Design Validation Using Verification Technology
Journal of Electronic Testing: Theory and Applications
New Techniques for Deterministic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach
Journal of Electronic Testing: Theory and Applications
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface
Journal of Electronic Testing: Theory and Applications
Testability Implications of Performance-Driven Logic Synthesis
IEEE Design & Test
Simulation-Based Engineering for Industrial Competitive Advantage
IEEE Design & Test
Efficient Sequential Test Generation Based on Logic Simulation
IEEE Design & Test
Application of Homing Sequences to Synchronous Sequential Circuit Testing
IEEE Transactions on Computers
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
Genetics-Based Learning of New Heuristics: Rational Scheduling of Experiments and Generalization
IEEE Transactions on Knowledge and Data Engineering
SETN '02 Proceedings of the Second Hellenic Conference on AI: Methods and Applications of Artificial Intelligence
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Transformation-Based Verification Using Generalized Retiming
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
DFT guidance through RTL test justification and propagation analysis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Static test sequence compaction based on segment reordering and accelerated vector restoration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On automatic generation of RTL validation test benches using circuit testing techniques
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
Software transformations for sequential test generation
ATS '95 Proceedings of the 4th Asian Test Symposium
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Improved sequential ATPG using functional observation information and new justification methods
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Alternating Strategies for Sequential Circuit ATPG
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Advanced Techniques for GA-based sequential ATPGs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An RTL Methodology to Enable Low Overhead Combinational Testing
EDTC '97 Proceedings of the 1997 European conference on Design and Test
New Static Compaction Techniques of Test Sequences for Sequential Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation
ETW '00 Proceedings of the IEEE European Test Workshop
Dynamic test compaction for synchronous sequential circuits using static compaction techniques
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
A genetic approach to test application time reduction for full scan and partial scan circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Dynamic test Sequence compaction for Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On Full Reset as a Design-For-Testability Technique
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
On the Detection of Reset Faults in Synchronous Sequential Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Deriving Signal Constraints to Accelerate Sequential Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Characterization and Implicit Identification of Sequential Indistinguishability
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Diagnostic Test Pattern Generation for Sequential Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Testability of Sequential Circuits with Multi-Cycle False Paths
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A Novel Solution for Chip-Level Functional Timing Verification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
8.2 On Synchronizing Sequences and Test Sequence Partitioning
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Techniques to Encode and Compress Fault Dictionaries
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On the Evaluation of Arbitrary Defect Coverage of Test Sets
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
RT-level TPG Exploiting High-Level Synthesis Information
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Diagnostic Test Generation for Sequential Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Fast Test Generation for Circuits with RTL and Gate-Level Views
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Combinational Test Generation for Various Classes of Acyclic Sequential Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Putting the Squeeze on Test Sequences
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Sequential Test Generation with Advanced Illegal State Search
ITC '97 Proceedings of the 1997 IEEE International Test Conference
BART: A Bridging Fault Test Generator for Sequential Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Technique for Identifying RTL and Gate-Level Correspondences
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Efficient Hierarchical Approach to Test Generation for Digital Systems
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Fault Simulation of IDDQ Tests for Bridging Faults in Sequential Circuits
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
LOCSTEP: A Logic Simulation-Based Test Generation Procedure
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Testing strategies for networks on chip
Networks on chip
SymSim: Symbolic Fault Simulation of Data- ow Data-path Designs at the Register-Transfer Level
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testability of the Philips 80C51 Micro-controller
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
Test vector decomposition-based static compaction algorithms for combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Evaluation of heuristic techniques for test vector ordering
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Fast Computation of Data Correlation Using BDDs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A New Approach to Test Generation and Test Compaction for Scan Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Application of Arithmetic Coding to Compression of VLSI Test Data
IEEE Transactions on Computers
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IEEE Transactions on Computers
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Diagnostic modelling of digital systems with multi-level decision diagrams
MS'06 Proceedings of the 17th IASTED international conference on Modelling and simulation
IEEE Transactions on Computers
Low test application time resource binding for behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Mixed hierarchical-functional fault models for targeting sequential cores
Journal of Systems Architecture: the EUROMICRO Journal
Double-single stuck-at faults: a delay fault model for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A complete testing strategy based on interacting and hierarchical FSMs
Integration, the VLSI Journal
Serial diagnostic fault simulation for synchronous sequential circuits
Integration, the VLSI Journal
TOV: sequential test generation by ordering of test vectors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing the storage requirements of a test sequence by using a background vector
Proceedings of the Conference on Design, Automation and Test in Europe
Transforming behavioral specifications to facilitate synthesis of testable designs
ITC'94 Proceedings of the 1994 international conference on Test
An automatic test pattern generator for large sequential circuits based on genetic algorithms
ITC'94 Proceedings of the 1994 international conference on Test
Hybrid design for testability combining scan and clock line control and method for test generation
ITC'94 Proceedings of the 1994 international conference on Test
Behavioral test generation using mixed integer non-linear programming
ITC'94 Proceedings of the 1994 international conference on Test
Full symbolic ATPG for large circuits
ITC'94 Proceedings of the 1994 international conference on Test
On synthesizing circuits with implicit test ability constraints
ITC'94 Proceedings of the 1994 international conference on Test
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic fault dictionaries and two-stage fault isolation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coverage-Directed Test Generation Automated by Machine Learning -- A Review
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic test pattern generation with BOA
PPSN'06 Proceedings of the 9th international conference on Parallel Problem Solving from Nature
Debugging with dominance: on-the-fly RTL debug solution implications
Proceedings of the International Conference on Computer-Aided Design
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
High performance MAC unit for DSP and cryptographic applications
ACM SIGARCH Computer Architecture News
Non-solution implications using reverse domination in a modern SAT-based debugging environment
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.04 |
This paper presents HITEC, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state. Several new techniques are introduced to improve the performance of test generation. A targeted D element technique is presented, which greatly increases the number of possible mandatory assignments and reduces the over-specification of state variables which can sometimes result when using a standard PODEM algorithm. A technique to use the state knowledge of previously generated vectors for state justification, without the memory overhead of a state transition diagram is presented. For faults that were aborted during the standard test generation phase, knowledge that was gained about fault propagation, by the fault simulator, is used. These techniques, when used together, produce the best published results for the ISCAS89 sequential benchmark circuits.