Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Speed up of behavioral A.T.P.G. using a heuristic criterion
DAC '93 Proceedings of the 30th international Design Automation Conference
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Binary decision diagrams and applications for VLSI CAD
Binary decision diagrams and applications for VLSI CAD
Sequential circuit test generation using decision diagram models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Test Synthesis with Alternative Graphs
IEEE Design & Test
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
DOT: New Deterministic Defect-Oriented ATPG Tool
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
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To cope with the complexity of today's digital systems in diagnostic modelling, hierarchical approaches should be used. In this paper, the possibilities of using Decision Diagrams (DD) for diagnostic modelling of digital systems are discussed. DDs can be used for modelling systems at different levels of representation like logic level, register transfer level, instruction set level. The nodes in DDs can be modelled as generic locations of faults. For more precise general specification of faults logic constraints are used. To map the physical defects from transistor level to logic level a new functional fault model is introduced.