Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A hierarchical test generation methodology for digital circuits
Journal of Electronic Testing: Theory and Applications
Hierarchical test generation under intensive global functional constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Functional fault modeling and simulation for VLSI devices
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
How many decomposition types do we need? [decision diagrams]
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Improving topological ATPG with symbolic techniques
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Cycle-based simulation with decision diagrams
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Sequential circuit test generation using decision diagram models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Timing simulation of digital circuits with binary decision diagrams
Proceedings of the conference on Design, automation and test in Europe
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Efficient Hierarchical Approach to Test Generation for Digital Systems
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Assertion-based automated functional vectors generation using constraint logic programming
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A New Testability Calculation Method to Guide RTL Test Generation
Journal of Electronic Testing: Theory and Applications
Diagnostic modelling of digital systems with multi-level decision diagrams
MS'06 Proceedings of the 17th IASTED international conference on Modelling and simulation
Mixed hierarchical-functional fault models for targeting sequential cores
Journal of Systems Architecture: the EUROMICRO Journal
PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams
Journal of Electronic Testing: Theory and Applications
Development of tests for VLSI circuit testability at the upper design levels
Automation and Remote Control
Predicate abstraction of RTL verilog descriptions using constraint logic programming
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Applying constraint logic programming to predicate abstraction of RTL verilog descriptions
MICAI'05 Proceedings of the 4th Mexican international conference on Advances in Artificial Intelligence
Efficient single-pattern fault simulation on structurally synthesized BDDs
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
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A new, generalized approach on the basis of alternative graphs (AG) to test synthesis and analysis for digital systems is proposed. AGs permit an efficient uniform model for describing the structure, functions, as well faults in a wide class of digital circuits at different representation levels. This model also supports a wide class of test design tasks--test generation, two- or multivalued simulation, test quality analysis, statistical fault grading, testability analysis, etc. Unlike the known methods, the proposed AG approach allows the use of a single uniform model library for solving these tasks.