Efficient single-pattern fault simulation on structurally synthesized BDDs

Authors:
Jaan Raik;Raimund Ubar;Sergei Devadze;Artur Jutman
Affiliations:
Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia;Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia;Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia;Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia
Venue:
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Year:
2005

Citing 3
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Abstract

Current paper proposes an efficient alternative for traditional gate-level fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSBDD) can be used for representation, simulation and fault modeling of digital circuits. It is shown how the first phase of any fault simulation algorithm: the fault-free simulation can be accelerated using this model. Moreover, it is pointed out that simultaneous to simulation on SSBDDs, the set of potential fault locations can be significantly reduced. In addition, algorithms for deductive and concurrent fault simulation on SSBDD models are introduced in the paper. While full implementation of the new SSBDD based algorithms needs to be carried out, the paper presents experimental data revealing the advantages of the proposed data structure in the fault simulation process.