Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
BDD based decomposition of logic functions with application to FPGA synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
The Size of Reduced OBDD's and Optimal Read-Once Branching Programs for Almost all Boolean Functions
IEEE Transactions on Computers
Incorporating speculative execution in exact control-dependent scheduling
DAC '94 Proceedings of the 31st annual Design Automation Conference
Hot-carrier reliability enhancement via input reordering and transistor sizing
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification techniques for cache coherence protocols
ACM Computing Surveys (CSUR)
Solving Boolean Equations Using ROSOP Forms
IEEE Transactions on Computers
The Theory of Zero-Suppressed BDDs and the Number of Knight‘s Tours
Formal Methods in System Design
Ordered Binary Decision Diagrams and Minimal Trellises
IEEE Transactions on Computers
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines
Formal Methods in System Design
Embryonics: A Bio-Inspired Cellular Architecture with Fault-Tolerant Properties
Genetic Programming and Evolvable Machines
Least Upper Bounds on OBDD Sizes
IEEE Transactions on Computers
Formal Verification Using Edge-Valued Binary Decision Diagrams
IEEE Transactions on Computers
Exploiting Transition Locality in Automatic Verification
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Implementation of Relational Algebra Using Binary Decision Diagrams
ReIMICS '01 Revised Papers from the 6th International Conference and 1st Workshop of COST Action 274 TARSKI on Relational Methods in Computer Science
Automata and Binary Decision Diagrams
WIA '98 Revised Papers from the Third International Workshop on Automata Implementation
Switch level hot-carrier reliability enhancement of VLSI circuits
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A New Testability Calculation Method to Guide RTL Test Generation
Journal of Electronic Testing: Theory and Applications
Boolean equation solving as graph traversal
CATS '06 Proceedings of the 12th Computing: The Australasian Theroy Symposium - Volume 51
Better upper bounds on the QOBDD size of integer multiplication
Discrete Applied Mathematics
First CPIR protocol with data-dependent computation
ICISC'09 Proceedings of the 12th international conference on Information security and cryptology
A hybrid fault simulator for synchronous sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
On the relative efficiency of DPLL and OBDDs with axiom and join
CP'11 Proceedings of the 17th international conference on Principles and practice of constraint programming
Efficient single-pattern fault simulation on structurally synthesized BDDs
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
BDD-Based Synthesis of Reversible Logic
International Journal of Applied Metaheuristic Computing
Boolean equation solving as graph traversal
CATS '06 Proceedings of the Twelfth Computing: The Australasian Theory Symposium - Volume 51
| Hi-index | 15.00 |
The behavior of ordered binary decision diagrams (OBDD) for general Boolean functions is studied. A tight upper bound of (2/sup n//n)(2+ epsilon ) for the worst case OBDD size is derived. Although the size of an OBDD is dependent on the ordering of decision variables, it is shown that almost all functions are not sensitive to variable ordering.