Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
A class of compatible cache consistency protocols and their support by the IEEE futurebus
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Correct memory operation of cache-based multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Hierarchical cache/bus architecture for shared memory multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
The cache coherence problem in shared-memory multiprocessors
The cache coherence problem in shared-memory multiprocessors
Efficient and correct execution of parallel programs that share memory
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reasoning about networks with many identical finite state processes
Information and Computation
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
A structural induction theorem for processes
Proceedings of the eighth annual ACM Symposium on Principles of distributed computing
Access ordering and coherence in shared memory multiprocessors
Access ordering and coherence in shared memory multiprocessors
Memory Access Dependencies in Shared-Memory Multiprocessors
IEEE Transactions on Software Engineering
Finding the Optimal Variable Ordering for Binary Decision Diagrams
IEEE Transactions on Computers
Verifying properties of large sets of processes with network invariants
Proceedings of the international workshop on Automatic verification methods for finite state systems
What are the limits of model checking methods for the verification of real life protocols?
Proceedings of the international workshop on Automatic verification methods for finite state systems
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Design and validation of computer protocols
Design and validation of computer protocols
Computer
Lockup-free caches in high-performance multiprocessors
Journal of Parallel and Distributed Computing
Performance evaluation of memory consistency models for shared-memory multiprocessors
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Proving sequential consistency of high-performance shared memories (extended abstract)
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Comparative evaluation of latency reducing and tolerating techniques
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Delayed consistency and its effects on the miss rate of parallel programs
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Reasoning about parallel architectures
Reasoning about parallel architectures
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
On the OBDD-Representation of General Boolean Functions
IEEE Transactions on Computers
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
The verification of cache coherence protocols
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
The Size of Reduced OBDD's and Optimal Read-Once Branching Programs for Almost all Boolean Functions
IEEE Transactions on Computers
Combined performance gains of simple cache protocol extensions
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Symbolic state model: a new approach for the verification of cache coherence protocols
Symbolic state model: a new approach for the verification of cache coherence protocols
Proving circuit correctness using formal comparison between expected and extracted behaviour
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
Automatic compositional minimization in CTL model checking
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Weak ordering—a new definition
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Communicating sequential processes
Communications of the ACM
A Unified Formalization of Four Shared-Memory Models
IEEE Transactions on Parallel and Distributed Systems
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Formal Verification of Delayed Consistency Protocols
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
The Cache Coherence Protocol of the Data Diffusion Machine
PARLE '89 Proceedings of the Parallel Architectures and Languages Europe, Volume I: Parallel Architectures
Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study
Euro-Par '95 Proceedings of the First International Euro-Par Conference on Parallel Processing
Using Partial Orders to Improve Automatic Verification Methods
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Verifying Temporal Properties of Sequential Machines Without Building their State Diagrams
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order Logic
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
A Top Down Approach to the Formal Specification of SCI Cache Coherence
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
Bounded-memory Algorithms for Verification On-the-fly
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
Generating BDDs for Symbolic Model Checking in CCS
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Higher-Level Specification and Verification with BDDs
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Automatic Reduction in CTL Compositional Model Checking
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Reliable Hashing without Collosion Detection
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Exploiting Symmetry In Temporal Logic Model Checking
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
A Tool for Symbolic Program Verification and Abstration
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Verification of a Distributed Cache Memory by Using Abstractions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Verification of the Futurebus+ Cache Coherence Protocol
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Efficient Verification with BDDs using Implicitly Conjoined Invariants
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Dynamic decentralized cache schemes for mimd parallel processors
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Lamport clocks: verifying a directory cache-coherence protocol
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Design Verification of the S3.mp Cache-Coherent Shared-Memory System
IEEE Transactions on Computers
Formal verification of complex coherence protocols using symbolic state models
Journal of the ACM (JACM)
Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models
IEEE Transactions on Parallel and Distributed Systems
Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol
IEEE Transactions on Parallel and Distributed Systems
Formal Verification of Coherence for a Shared Memory Multiprocessor Model
PaCT '01 Proceedings of the 6th International Conference on Parallel Computing Technologies
Modelling and Model Checking a Distributed Shared Memory Consistency Protocol
ICATPN '98 Proceedings of the 19th International Conference on Application and Theory of Petri Nets
Using Timestamping and History Variables to Verify Sequential Consistency
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Constraint-Based Verification of Parameterized Cache Coherence Protocols
Formal Methods in System Design
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
IEEE/ACM Transactions on Networking (TON)
Formal Verification and its Impact on the Snooping versus Directory Protocol Debate
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Fair Model Checking with Process Counter Abstraction
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Real-time event handling in an RFID middleware system
DNIS'07 Proceedings of the 5th international conference on Databases in networked information systems
On-chip COMA cache-coherence protocol for microgrids of microthreaded cores
Euro-Par'07 Proceedings of the 2007 conference on Parallel processing
Reachability as derivability, finite countermodels and verification
ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
Verifying safety of a token coherence implementation by parametric compositional refinement
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Context-Bounded model checking of concurrent software
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Manager-client pairing: a framework for implementing coherence hierarchies
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Towards the formal verification of cache coherency at the architectural level
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
The Journal of Supercomputing
High-performance fractal coherence
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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In this article we present a comprehensive survey of various approaches for the verification of cache coherence protocols based on state enumeration, (symbolic model checking, and symbolic state models. Since these techniques search the state space of the protocol exhaustively, the amount of memory required to manipulate that state information and the verification time grow very fast with the number of processors and the complexity of the protocol mechanisms. To be successful for systems of arbitrary complexity, a verification technique must solve this so-called state space explosion problem. The emphasis of our discussion is onthe underlying theory in each method of handling the state space exposion problem, and formulationg and checking the safety properties (e.g., data consistency) and the liveness properties (absence of deadlock and livelock). We compare the efficiency and discuss the limitations of each technique in terms of memory and computation time. Also, we discuss issues of generality, applicability, automaticity, and amenity for existing tools in each class of methods. No method is truly superior because each method has its own strengths and weaknesses. Finally, refinements that can further reduce the verification time and/or the memory requirement are also discussed.