Memory Access Dependencies in Shared-Memory Multiprocessors

  • Authors:
  • Michel Dubois;Christoph Scheurich

  • Affiliations:
  • Univ. of Southern California, Los Angeles;Univ. of Southern California, Los Angeles

  • Venue:
  • IEEE Transactions on Software Engineering
  • Year:
  • 1990

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Abstract

The presence of high-performance mechanisms in shared-memory multiprocessors such as private caches, the extensive pipelining of memory access, and combining networks may render a logical concurrency model complex to implement or inefficient. The problem of implementing a given logical concurrency model in such a multiprocessor is addressed. Two concurrency models are considered, and simple rules are introduced to verify that a multiprocessor architecture adheres to the models. The rules are applied to several examples of multiprocessor architectures.