Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Memory Access Dependencies in Shared-Memory Multiprocessors
IEEE Transactions on Software Engineering
Proving sequential consistency of high-performance shared memories (extended abstract)
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Reasoning about parallel architectures
Reasoning about parallel architectures
Programming DEC-Alpha based multiprocessors the easy way (extended abstract)
SPAA '94 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures
Designing memory consistency models for shared-memory multiprocessors
Designing memory consistency models for shared-memory multiprocessors
Memory consistency models for shared-memory multiprocessors
Memory consistency models for shared-memory multiprocessors
SIAM Journal on Computing
Commit-reconcile & fences (CRF): a new memory model for architects and compiler writers
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Weak ordering—a new definition
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A Unified Formalization of Four Shared-Memory Models
IEEE Transactions on Parallel and Distributed Systems
Specifying memory consistency of write buffer multiprocessors
ACM Transactions on Computer Systems (TOCS)
What is Itanium Memory Consistency from the Programmer's Point of View?
Electronic Notes in Theoretical Computer Science (ENTCS)
The semantics of x86-CC multiprocessor machine code
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
The semantics of power and ARM multiprocessor machine code
Proceedings of the 4th workshop on Declarative aspects of multicore programming
Understanding POWER multiprocessors
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Automatic inference of memory fences
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Programmer-centric conditions for itanium memory consistency
ICDCN'06 Proceedings of the 8th international conference on Distributed Computing and Networking
DISC'06 Proceedings of the 20th international conference on Distributed Computing
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Fences in weak memory models (extended version)
Formal Methods in System Design
An axiomatic memory model for POWER multiprocessors
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
A formal hierarchy of weak memory models
Formal Methods in System Design
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This paper introduces a generic framework for defining instructions, programs, and the semantics of their instantiation by operations in a multiprocessor environment. The framework captures information flow between operations in a multiprocessor program by means of a reads-from mapping from read operations to write operations. Two fundamental relations are defined on the operations: a program order between operations which instantiate the program of some processor and view orders which are specific to each shared memory model. An operation cannot read from the 驴hidden驴past or from the future; the future and the past causality can be examined either relative to the program order or relative to the view orders. A shared memory model specifies, for a given program, the permissible transformation of resource states. The memory model should reflect the programmer's view by citing the guaranteed behavior of the multiprocessor in the interface visible to the programmer. The model should refrain from dictating the design practices that should be followed by the implementation. Our framework allows an architect to reveal the programming view induced by a shared-memory architecture; it serves programmers exploring the limits of the programming interface and guides architecture-level verification. The framework is applicable for complex, commercial architectures as it can capture subtle programming-interface details, exposing the underlying aggressive microarchitecture mechanisms. As an illustration, we define the shared memory model supported by the PowerPC architecture, within our framework.