The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture
IEEE Transactions on Parallel and Distributed Systems
Towards a Formal Model of Shared Memory Consistency for Intel Itanium(tm)
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Memory Model = Instruction Reordering + Store Atomicity
Proceedings of the 33rd annual international symposium on Computer Architecture
Translating between itanium and sparc memory consistency models
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Specifying memory consistency of write buffer multiprocessors
ACM Transactions on Computer Systems (TOCS)
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A programmer-centric model describes the memory consistency rules of amultiprocessor as a collection, one for each processor, of 'views' of instructions and some agreements between these views. It also requires the natural notion of validity: the value read from a shared memory location is the one that was most recently stored, according to a given view. This allows reasoning about programs at a non-operational level in the natural way, not obscured by the implementation details of the underlying architecture. In this paper, we formulate a programmer-centric description of the memory consistency model provided by the Itanium architecture. However, our definition is not tight. We provide two very similar definitions and show that the specification of the Itanium memory model lies between the two. These two definitions are motivated by slightly different implementations of load-acquire instructions. A further entertainment of a handful of other load-acquire rules leads us to question whether the specification of the Itanium memory order [Intel Corporation. A formal specification of the intel itanium processor family memory ordering. http://www.intel.com/, Oct 2002] is indeed faithful to the Itanium architecture intentions.