Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Advances in Petri nets 1986, part II on Petri nets: applications and relationships to other models of concurrency
Reasoning about parallel architectures
Reasoning about parallel architectures
The power of processor consistency
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
An executable specification, analyzer and verifier for RMO (relaxed memory order)
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture
IEEE Transactions on Parallel and Distributed Systems
Memory consistency models for high-performance distributed computing
Memory consistency models for high-performance distributed computing
Memory consistency models for high-performance distributed computing
Memory consistency models for high-performance distributed computing
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
CheckFence: checking consistency of concurrent data types on relaxed memory models
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How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
Reasoning about the ARM weakly consistent memory model
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Formalising java's data race free guarantee
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Programmer-centric conditions for itanium memory consistency
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The semantics of power and ARM multiprocessor machine code
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Verified LISP Implementations on ARM, x86 and PowerPC
TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
A Better x86 Memory Model: x86-TSO
TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
Verified just-in-time compiler on x86
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Analyzing multicore dumps to facilitate concurrency bug reproduction
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x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
Communications of the ACM
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PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
MemSAT: checking axiomatic specifications of memory models
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Memory, an elusive abstraction
Proceedings of the 2010 international symposium on Memory management
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Reasoning about the implementation of concurrency abstractions on x86-TSO
ECOOP'10 Proceedings of the 24th European conference on Object-oriented programming
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Laws of order: expensive synchronization in concurrent algorithms cannot be eliminated
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
WOMM: a weak operational memory model
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part I
Understanding POWER multiprocessors
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Partial-coherence abstractions for relaxed memory models
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
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Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Automatic inference of memory fences
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ITP'11 Proceedings of the Second international conference on Interactive theorem proving
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Science of Computer Programming
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
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CC'10/ETAPS'10 Proceedings of the 19th joint European conference on Theory and Practice of Software, international conference on Compiler Construction
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ESOP'10 Proceedings of the 19th European conference on Programming Languages and Systems
Generative operational semantics for relaxed memory models
ESOP'10 Proceedings of the 19th European conference on Programming Languages and Systems
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ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
From total store order to sequential consistency: a practical reduction theorem
ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
Fences in weak memory models (extended version)
Formal Methods in System Design
RockSalt: better, faster, stronger SFI for the x86
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
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A formal hierarchy of weak memory models
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Plan B: a buffered memory model for Java
POPL '13 Proceedings of the 40th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
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Journal of the ACM (JACM)
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| Hi-index | 0.02 |
Multiprocessors are now dominant, but real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, they have subtle relaxed (or weak) memory models, usually described only in ambiguous prose, leading to widespread confusion. We develop a rigorous and accurate semantics for x86 multiprocessor programs, from instruction decoding to relaxed memory model, mechanised in HOL. We test the semantics against actual processors and the vendor litmus-test examples, and give an equivalent abstract-machine characterisation of our axiomatic memory model. For programs that are (in some precise sense) data-race free, we prove in HOL that their behaviour is sequentially consistent. We also contrast the x86 model with some aspects of Power and ARM behaviour. This provides a solid intuition for low-level programming, and a sound foundation for future work on verification, static analysis, and compilation of low-level concurrent code.