Reasoning about parallel architectures
Reasoning about parallel architectures
How to Make a Correct Multiprocess Program Execute Correctly on a Multiprocessor
IEEE Transactions on Computers
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Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
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Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
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Queue - Concurrency
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This paper describes a formalization of the ARM weakly consistent memory model: the architectural contract between parallel programs and shared memory multiprocessor implementations. We claim that a clean, unambiguous, and mechanically verifiable specification is a valuable resource for architects, micro-architects and programmers; it allows implementors to forge aggressive static (compiler) and dynamic (JIT, micro-architecture) machines to run code. We discuss the key construct of the ARM memory model, observability -- the order in which memory accesses become visible to processors in a shared memory multiprocessor system -- and examine its use in litmus tests.