Parallel assertions for architectures with weak memory models

Authors:
Daniel Schwartz-Narbonne;Georg Weissenbacher;Sharad Malik
Affiliations:
Princeton University;Princeton University, USA,Vienna University of Technology, Austria;Princeton University
Venue:
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
Year:
2012

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Abstract

Assertions are a powerful and widely used debugging tool in sequential programs, but are ineffective at detecting concurrency bugs. We recently introduced parallel assertions which solve this problem by providing programmers with a simple and powerful tool to find bugs in parallel programs. However, while modern computer hardware implements weak memory models, the sequentially consistent semantics of parallel assertions prevents these assertions from detecting some feasible bugs. We present a formal semantics for parallel assertions that accounts for the effects of weak memory models. This new formal semantics allows us to prove the correctness of two key optimizations which significantly increase the speed of a runtime assertion checker on a set of PARSEC benchmarks. We discuss the probe effect caused by checking these assertions at runtime, and show how our new semantics allows the detection of bugs that were undetectable in the previous semantics.