IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Eraser: a dynamic data race detector for multithreaded programs
ACM Transactions on Computer Systems (TOCS)
Proceedings of the 1998 ACM SIGSOFT international symposium on Software testing and analysis
An Executable Specification and Verifier for Relaxed Memory Order
IEEE Transactions on Computers - Special issue on cache memory and related problems
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Correction of a Memory Management Method for Lock-Free Data Structures
Correction of a Memory Management Method for Lock-Free Data Structures
Scalable lock-free dynamic memory allocation
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
DCAS is not a silver bullet for nonblocking algorithm design
Proceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures
Fast and lock-free concurrent priority queues for multi-thread systems
Journal of Parallel and Distributed Computing
Software and the Concurrency Revolution
Queue - Multiprocessors
CheckFence: checking consistency of concurrent data types on relaxed memory models
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Memory model sensitive analysis of concurrent data types
Memory model sensitive analysis of concurrent data types
Atomizer: A dynamic atomicity checker for multithreaded programs
Science of Computer Programming
Race directed random testing of concurrent programs
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Static analysis via abstract interpretation of the happens-before memory model
TAP'08 Proceedings of the 2nd international conference on Tests and proofs
Partial-coherence abstractions for relaxed memory models
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Automatic inference of memory fences
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
A verification-based approach to memory fence insertion in relaxed memory systems
Proceedings of the 18th international SPIN conference on Model checking software
Dynamic synthesis for relaxed memory models
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
Parallel assertions for architectures with weak memory models
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
A verification-based approach to memory fence insertion in PSO memory systems
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
CDSchecker: checking concurrent data structures written with C/C++ atomics
Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications
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Several concurrent implementations of familiar data abstractions such as queues, sets, or maps typically do not follow locking disciplines, and often use lock-free synchronization to gain performance. Since such algorithms are exposed to a weak memory model, they are notoriously hard to get correct, as witnessed by many bugs found in published algorithmsWe outline a technique for analyzing correctness of concurrent algorithms under weak memory models, in which a model checker is used to search for correctness violations. The algorithm to be analyzed is transformed into a form where statements may be reordered according to a particular weak memory ordering. The transformed algorithm can then be analyzed by a model-checking tool, e.g., by enumerative state exploration. We illustrate the approach on a small example of a queue, which allows an enqueue operation to be concurrent with a dequeue operation, which we analyze with respect to the RMO memory model defined in SPARC v9.